Principal Engineer, Hardware Systems & Silicon Validation

About Marvell

Marvells semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise cloud and AI and carrier architectures our innovative technology is enabling new possibilities.

At Marvell you can affect the arc of individual lives lift the trajectory of entire industries and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation above and beyond fleeting trends Marvell is a place to thrive learn and lead.

Your Team Your Impact

What You Can Expect

• Own responsibility for Marvell Ethernet Cu PHY Validation in post-silicon environment.
• Develop System-level and Silicon-level test plan for Marvell Alaska-M Ethernet PHY and Alaska-C HSC Retimer PHY products.
• Define document execute and report the overall PHY validation/test plan for Marvell storage devices.
• Lab-based silicon bring-up and unit test execution focused on 10BASE-T Physical and PCS layer hardware and firmware functionality.
• Perform high speed signal validation and analysis using various test equipment to measure Eye diagram/Jitter/BER.
• Analyze and debug issues on PHY protocol of storage interface (SERDES Ethernet).
• Troubleshoot failing tests using diagnostics software tools hardware analyzers oscilloscopes meters logic/protocol analyzers.
• Lead collaborative technical discussions to drive resolution on technical issues. Work with cross-functional teams and external vendors to debug any post-silicon and/or customer issues related to Cu PHY and High Speed SERDES Retimer PHY.
• Work closely with customers to address design issue and debug failure cases.

What Were Looking For

As a Principal Engineer in Hardware and Silicon Validation at Marvell you will play a key role in the development and delivery of Marvells Alaska-M and Alaska-C Ethernet PHY products. Your responsibilities will include validating high-performance networking hardware such as copper 10GBASE-T Ethernet PHYs and high-speed PAM4 SERDES retimer transceiverscritical technologies that enable high-density Ethernet switch applications across enterprise PoE wireless and data center environments.

• Bachelors degree in Computer Science Electrical Engineering or related fields and 10-15 years of related professional experience OR Masters degree and/or PhD in Computer Science Electrical Engineering or related fields with 5-10 years of experience.
• Strong understanding of high-speed SERDES equalization technique and Ethernet Networking protocols.
• 5 years of experience with High Speed IO testing Analog AFE characterization debugging and validation
• Strong lab skills with hands on experience in system bring up system testing and debug.
• In-depth working knowledge of test equipment used for PAM4 SERDES characterization and 10GBASE-T Cu PHY Ethernet AFE Analog ADC DAC characterization (Scope BERT Network analyzer Spectrum Analyser etc.).
• Strong analytical problem-solving and communication skills.

Preferred:

• Working knowledge of Ethernet Networking interface and characterization.
• Working knowledge and experience on Ethernet and PAM4 SERDES is a definite plus.
• Extensive knowledge of the physical and protocol levels (PMA PCS MAC) of one or more common high-speed interfaces is an asset.
• Working knowledge of hardware board design; able to read board schematics and board layout.
• Working experience with Python.

Expected Base Pay Range (USD)

The successful candidates starting base pay will be determined based on job-related skills experience qualifications work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

All qualified applicants will receive consideration for employment without regard to race color religion sex national origin sexual orientation gender identity disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at .

Interview Integrity

As part of our commitment to fair and authentic hiring practices we ask that candidates do not use AI tools (e.g. transcription apps real-time answer generators like ChatGPT CoPilot or note-taking bots) during interviews.

Our interviews are designed to assess your personal experience thought process and communication skills in real-time. If a candidate uses such tools during an interview they will be disqualified from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations including the Export Administration Regulations (EAR). As such applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens lawful permanent residents or protected individuals as defined by 8 U.S.C. 1324b(a)(3) all applicants may be subject to an export license review process prior to employment.