Join our team in a pivotal role where youll own the entire IP-level netlist generation and timing convergence journey from synthesis to sign-off. Youll drive synthesis UPF power intent scan insertion and external IP integration while architecting timing constraints for both standard and complex custom designs that ensure sign-off quality from day one. Working at the intersection of multiple disciplines youll partner closely with RTL designers to deeply understand design intent and clock architecture collaborate with CAD teams to shape and optimize cutting-edge flows and team with Physical Design engineers to achieve flawless timing sign-off. Were seeking an innovative thinker who brings fresh perspectives to timing analysis methodologies and proactively identifies and resolves timing challenges to eliminate pessimism and accelerate convergence ultimately making their mark on next-generation chip design.
- Bsc/Msc in Electrical Engineering
- 5 years of experience in the field
- At least 2 years of experience in writing ASIC timing constraints and achieving timing closure
- Expertise in STA tools (Primetime) and flow generation
- Knowledge of the ASIC design timing closure flow and methodology
- Understanding of timing corners/modes
- Familiarity with process variations and signal integrity-related issues
- Hands-on experience in generating and managing timing/SDC constraints proficient in scripting languages (Tcl and Perl)
- Knowledge of synthesis DFT and backend-related methodologies and tools
- Strong communication skills are required as you will interact with various groups
Join our team in a pivotal role where youll own the entire IP-level netlist generation and timing convergence journey from synthesis to sign-off. Youll drive synthesis UPF power intent scan insertion and external IP integration while architecting timing constraints for both standard and complex cust...
Join our team in a pivotal role where youll own the entire IP-level netlist generation and timing convergence journey from synthesis to sign-off. Youll drive synthesis UPF power intent scan insertion and external IP integration while architecting timing constraints for both standard and complex custom designs that ensure sign-off quality from day one. Working at the intersection of multiple disciplines youll partner closely with RTL designers to deeply understand design intent and clock architecture collaborate with CAD teams to shape and optimize cutting-edge flows and team with Physical Design engineers to achieve flawless timing sign-off. Were seeking an innovative thinker who brings fresh perspectives to timing analysis methodologies and proactively identifies and resolves timing challenges to eliminate pessimism and accelerate convergence ultimately making their mark on next-generation chip design.
- Bsc/Msc in Electrical Engineering
- 5 years of experience in the field
- At least 2 years of experience in writing ASIC timing constraints and achieving timing closure
- Expertise in STA tools (Primetime) and flow generation
- Knowledge of the ASIC design timing closure flow and methodology
- Understanding of timing corners/modes
- Familiarity with process variations and signal integrity-related issues
- Hands-on experience in generating and managing timing/SDC constraints proficient in scripting languages (Tcl and Perl)
- Knowledge of synthesis DFT and backend-related methodologies and tools
- Strong communication skills are required as you will interact with various groups
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