ASIC Design Engineer Cache Controller

Santa Clara County, CA - USA

Monthly Salary: Not Disclosed

Posted on: 03-11-2025

Vacancies: 1 Vacancy

Job Summary

In-depth knowledge of memory subsystem
Academic experience with RTL/micro-architecture development
Good understanding of PPA (performance/power/area) tradeoffs
B.S. in a relevant field 0 years of industry experience

Cache design background including good understanding of different memory organizations and tradeoffs
Experience with multi-processor cache coherence protocols
Knowledge of high-performance coherent memory systems or interconnect architectures
Knowledge of high-performance DRAM controller
M.S in a relevant field.

In-depth knowledge of memory subsystemAcademic experience with RTL/micro-architecture developmentGood understanding of PPA (performance/power/area) tradeoffsB.S. in a relevant field 0 years of industry experienceCache design background including good understanding of different memory organizations ...

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