Senior Principal DFT Design Engineer

Cadence Systems

Not Interested
Bookmark
Report This Job

profile Job Location:

Austin, TX - USA

profile Monthly Salary: USD 5 - 15
Posted on: 28 days ago
Vacancies: 1 Vacancy

Job Summary

At Cadence we hire and develop leaders and innovators who want to make an impact on the world of technology.

We are looking for SoC/ASIC Digital Design Engineer with experience in Design for Test (DFT). An intimate knowledge and experience in scan chain insertion compression scan technologies memory built-in self-test (MBIST) and automatic test pattern generation (ATPG) is required for this position. Should follow systematic quality metrics driven ATPG pattern generation. It is highly desirable for candidate to possess hands-on knowledge of synthesis verification and debugging Verilog testbenches.

Requirements;

US citizenship preferred.

  • Prior 5-15 years of professional experience in SoC/ASIC Digital Design with focus on Design for Test (DFT)
  • Should possess intimate knowledge of DFT insertion flows
  • Basic scan chain insertion using synthesis or other software tools
  • Experience in compression scan insertion LBIST and other scan technologies
  • Intimate knowledge of memory build-in self-test (MBIST)
  • Expertise in Automatic Test Pattern Generation (ATPG) to achieve design test coverage goals
  • Debug and Analysis of failures to improve fault coverage
  • Verification of ATPG testbenches and debugging root cause of simulation mis-compares
  • Working knowledge of JTAG 1149.1/6 IEEE1500 and IEEE1687
  • Knowledge of timing analysis and equivalency checks would be added bonus
  • Ability to work in collaborative team environment
  • Prior experience with Cadence tools and flows is highly desirable
  • Should be able to finish DFT tasks independently
  • Strong problem-solving skills. Exhibit discipline thoroughness and methodical approach in solving problems
  • Ability to work with stakeholders across cross-functional teams Architecture Design Internal and External Customers
  • Self-driven and committed individual who can work in a fast-paced project environment

Were doing work that matters. Help us solve what others cant.


Required Experience:

Staff IC

At Cadence we hire and develop leaders and innovators who want to make an impact on the world of technology.We are looking for SoC/ASIC Digital Design Engineer with experience in Design for Test (DFT). An intimate knowledge and experience in scan chain insertion compression scan technologies memory ...
View more view more

Key Skills

  • GP
  • Maintenance Planning
  • ASP.NET
  • Food Processing
  • Catia

About Company

Company Logo

Do you want to shape the future of technology? Cadence is leading the charge to solve some of technology’s toughest challenges. We work with the world’s most innovative companies, across a growing range of industries. Major trends that you hear about everyday – like artificial intell ... View more

View Profile View Profile