Sr RTL Design Engineer (Floating Point Architecture)
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Job Location:
Hillsboro, IL - USA
Monthly Salary:
$ 140000 - 160000
Posted on:
01-11-2025
Vacancies:
1 Vacancy
Job Summary
Job Title: Senior RTL Design Engineer Floating Point Architecture
Location: Remote (Anywhere in USA)
Full-time: Salary Benefits Bonuses
About the Role
We are seeking a Senior RTL Design Engineer with strong expertise in floating-point datapath design to join our high-performance silicon design team. The ideal candidate will have a proven track record in architecting implementing and verifying complex digital designs in ASIC or FPGA environments with a particular focus on floating-point units (FPUs) arithmetic pipelines and high-speed compute blocks.
Key Responsibilities
Design and implement high-performance RTL modules using Verilog/SystemVerilog with emphasis on floating-point arithmetic datapath and control logic.
Collaborate with architecture and microarchitecture teams to define and optimize floating-point algorithms and hardware structures.
Perform detailed RTL coding linting synthesis and timing closure to achieve PPA (Performance Power Area) goals.
Work closely with verification engineers to ensure functional correctness and coverage of complex FP datapaths.
Drive micro-architecture definition design reviews and documentation of design specifications.
Collaborate with physical design DFT and firmware/software teams to ensure seamless integration and bring-up.
Participate in FPGA prototyping or emulation to validate functionality and performance.
Mentor junior engineers and contribute to best practices in RTL design and floating-point arithmetic implementation.
Required Qualifications
BS/MS/PhD in Electrical Engineering Computer Engineering or a related field.
8 years of experience in RTL design for ASIC or FPGA projects.
Strong understanding of floating-point standards (IEEE 754) rounding modes normalization and exception handling.
Proven experience in floating-point datapath design including adders multipliers dividers and fused operations.
Proficiency with Verilog/SystemVerilog synthesis tools (Synopsys Cadence Siemens) and lint/timing analysis tools.
Hands-on experience with simulation and debug tools (VCS QuestaSim Verdi etc.).
Knowledge of hardware performance optimization and trade-offs in latency area and power.
Preferred Qualifications
Experience with AI/ML accelerators DSP cores or GPU/CPU floating-point pipelines.
Familiarity with C/C or Python for modeling and validation of floating-point algorithms.
Exposure to UVM-based verification environments.
Background in high-speed design clock-domain crossing (CDC) and low-power methodologies.
Excellent problem-solving debugging and documentation skills.
The anticipated annual base salary for this position is between $140000 to $160000 which also includes a comprehensive benefits package.
Full-Time Benefits:
15 days of PTO per calendar year
10 paid Holidays per calendar year
Comprehensive Medical Benefits: Company covers 80% of premiums for Employee and Dependents
Dental & Vision: Company covers 50% of premiums for Employee and Dependents
Voluntary Benefits: Life Insurance FSA (Health and Dependent Limited Purpose) HAS and Gap Insurance
Employee Assistant Program (EAP)
401k - Traditional & Roth
Life/AD&D and Long-Term Disability
Tuition reimbursement
Equal Opportunity Policy Statement
Encore Semi Inc. is an Equal Opportunity Employer that does not discriminate on the basis of actual or perceived race religion creed color age sex sexual orientation gender gender identity or expression national origin genetics ancestry marital status civil union status medical condition disability (mental and physical) military and veteran status pregnancy childbirth and related medical conditions or any other characteristic protected by applicable federal state or local laws and ordinances.
Encore Semi is also committed to compliance with all fair employment practices regarding citizenship and immigration status.
Location: Remote (Anywhere in USA)
Full-time: Salary Benefits Bonuses
About the Role
We are seeking a Senior RTL Design Engineer with strong expertise in floating-point datapath design to join our high-performance silicon design team. The ideal candidate will have a proven track record in architecting implementing and verifying complex digital designs in ASIC or FPGA environments with a particular focus on floating-point units (FPUs) arithmetic pipelines and high-speed compute blocks.
Key Responsibilities
Design and implement high-performance RTL modules using Verilog/SystemVerilog with emphasis on floating-point arithmetic datapath and control logic.
Collaborate with architecture and microarchitecture teams to define and optimize floating-point algorithms and hardware structures.
Perform detailed RTL coding linting synthesis and timing closure to achieve PPA (Performance Power Area) goals.
Work closely with verification engineers to ensure functional correctness and coverage of complex FP datapaths.
Drive micro-architecture definition design reviews and documentation of design specifications.
Collaborate with physical design DFT and firmware/software teams to ensure seamless integration and bring-up.
Participate in FPGA prototyping or emulation to validate functionality and performance.
Mentor junior engineers and contribute to best practices in RTL design and floating-point arithmetic implementation.
Required Qualifications
BS/MS/PhD in Electrical Engineering Computer Engineering or a related field.
8 years of experience in RTL design for ASIC or FPGA projects.
Strong understanding of floating-point standards (IEEE 754) rounding modes normalization and exception handling.
Proven experience in floating-point datapath design including adders multipliers dividers and fused operations.
Proficiency with Verilog/SystemVerilog synthesis tools (Synopsys Cadence Siemens) and lint/timing analysis tools.
Hands-on experience with simulation and debug tools (VCS QuestaSim Verdi etc.).
Knowledge of hardware performance optimization and trade-offs in latency area and power.
Preferred Qualifications
Experience with AI/ML accelerators DSP cores or GPU/CPU floating-point pipelines.
Familiarity with C/C or Python for modeling and validation of floating-point algorithms.
Exposure to UVM-based verification environments.
Background in high-speed design clock-domain crossing (CDC) and low-power methodologies.
Excellent problem-solving debugging and documentation skills.
The anticipated annual base salary for this position is between $140000 to $160000 which also includes a comprehensive benefits package.
Full-Time Benefits:
15 days of PTO per calendar year
10 paid Holidays per calendar year
Comprehensive Medical Benefits: Company covers 80% of premiums for Employee and Dependents
Dental & Vision: Company covers 50% of premiums for Employee and Dependents
Voluntary Benefits: Life Insurance FSA (Health and Dependent Limited Purpose) HAS and Gap Insurance
Employee Assistant Program (EAP)
401k - Traditional & Roth
Life/AD&D and Long-Term Disability
Tuition reimbursement
Equal Opportunity Policy Statement
Encore Semi Inc. is an Equal Opportunity Employer that does not discriminate on the basis of actual or perceived race religion creed color age sex sexual orientation gender gender identity or expression national origin genetics ancestry marital status civil union status medical condition disability (mental and physical) military and veteran status pregnancy childbirth and related medical conditions or any other characteristic protected by applicable federal state or local laws and ordinances.
Encore Semi is also committed to compliance with all fair employment practices regarding citizenship and immigration status.
Required Experience:
Senior IC
Key Skills
- Aerospace Engineering
- Anti Money Laundering
- Electrical Installation
- Desktop Support
- Corporate Marketing
- Fabrication
About Company
Encore Semi provides engineering services and solutions to the Semiconductor and Electronics industries, using highly advanced technologies and tools. Our Teams of Engineers provide custom engineering solutions for semiconductor product companies, OEMs developing IP or SoC, and Subsy ... View more
