PHY Design Verification Engineer
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Job Location:
San Francisco, CA - USA
Monthly Salary:
Not Disclosed
Posted on:
18 days ago
Vacancies:
1 Vacancy
Job Summary
In this highly visible role you will be at the center of a silicon design group with a critical impact on delivering world-class silicon to empower wireless products for hundreds of millions of customers. As a PHY Design Verification Engineer you will be responsible for pre-silicon RTL verification of wireless PHY and its interfaces with the rest of the wireless communication SoC. You will interact with DV methodologists designers and communication systems engineers to develop reusable test bench and verification environment deploying the latest methodology with metric-driven verification ensuring the highest design quality.
- BS and a minimum of 10 years relevant industry experience
- Verification experience of wireless/wired communication block/subsystem.
- Advanced knowledge of Verilog SystemVerilog UVM and SystemVerilog Assertion.
- Excellent knowledge and experience of ASIC verification flows including test bench development constrained random testing and code/functional coverage.
- Experience of using Matlab/C reference model and bit-accurate verification.
- Verification experience of wireless/wired communication block/subsystem.
- Knowledge of wireless protocols such as Bluetooth UWB WLAN or Zigbee.
- Proficient in shell and Python scripting Perl scripting.
- Experience of using AI technologies in data mining/analysis.
- Experience of Palladium/FPGA validation.
- Should be a team player with excellent communication skills self-motivated and well organized.
Key Skills
- Arabic Speaking
- Logistics Operations
- Lecturing
- Community Support
- Gynaecology & Obstetrics
- AC Maintenance
About Company
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