Emulation Verification Engineer (Japan Design Center)
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Job Location:
Monthly Salary:
Posted on:
21 days ago
Vacancies:
1 Vacancy
Job Summary
As a member of Emulation verification team you will play a key role in using Emulation for verification of mixed signal SoCs which has large digital and analog sections. The individual will be responsible for porting the design to Emulation platform with the help of the Emulation team and then delivering the verification plan.
- 5 years of experience with bring up debugging and verification in Emulation
- Good understanding of any Standard Emulator (Palladium Veloce Zebu) OR FPGA (Xilinx Altera) flow
- Proven design verification skills
- Experience in writing Synthesize-able System Verilog/Verilog code and System Verilog assertions
- Experience on any Scripting (Perl/Python/TCL)
- Excellent analytical and debug skills
- Excellent oral and written English skills
- Experience with System Verilog verification environments including C/C DPI UVM
- Understanding of the tool flow from RTL to Emulation
- Experience in UVM Acceleration
Key Skills
- Arabic Speaking
- Logistics Operations
- Lecturing
- Community Support
- Gynaecology & Obstetrics
- AC Maintenance
About Company
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