PMU Analog Layout Designer
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Job Location:
Cupertino, CA - USA
Monthly Salary:
Not Disclosed
Posted on:
30+ days ago
Vacancies:
1 Vacancy
Job Summary
You will be responsible to deliver PDV clean layout this includes the following: Working with circuit design team to plan/schedule work and negotiate any necessary layout trade-offs as needed to build complex analog layout in deep SubMicron CMOS failure prone circuit and layout complete set of design verification tools available on Mega-cell level (also on chip level).Interpreting LVS DRC and ERC reports to find the fastest way to complete engineering specifications and expectations by working closely with the circuit design advanced CAD tools and mask design knowledge to deliver correct and robust layout that meet stringent matching performance area and power requirements.
- BS and a minimum of 3 years relevant industry experience.
- Relevant experience in analog/mixed-signal layout design of SubMicron CMOS circuits.
- Experience building tight matching low capacitance low power analog blocks resistors capacitors high voltage devices pad IOs ESD structures etc.
- Experience with custom and standard cell based floor planning and hierarchical layout assembly.
- Understanding of IR drop RC delay electro-migration self-heating and cross capacitance.
- Looking for relevant experience with analog and DFM practices.
- Experience in PMU and chip level layout is highly preferred.
- Scripting experience in PERL or SKILL CODE is considered a plus
- Excellent communication skills and able to work with multi-functional teams.
- Proficiency in interpretation of Calibre DRC ERC LVS etc. reports.
- Knowledge of MENTOR GRAPHICS or CADENCE layout tools.
- Masters Degree preferred
Key Skills
- Design Engineering
- Design
- Engineering
- Design Management
- Control System
About Company
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