As a CPU Microarchitect/RTL Engineer you will participate in the following: Micro-architecture development and specification - from early high-level architectural exploration through micro-architectural research and arriving at a detailed specification RTL ownership - development assessment and refinement of RTL design to target power performance area and timing goals Verification - support the verification team in test bench development formal methods and simulation/emulation for formal verification Performance exploration and correlation - explore high-performance strategies and work with the performance verification team to verify that the RTL design meets targeted performance Design delivery - work with multi-functional engineering team to implement and verify physical design on the aspects of timing area reliability testability and power
- Minimum BS
- Experience with at least one of the following languages: Verilog or VHDL
- Expertise in one or more of the following areas: instruction fetch and decode branch prediction; instruction scheduling and register renaming out-of-order execution; integer and floating point execution; load/store execution; cache and memory subsystems; machine-learning algorithms and mapping to hardware; or power and thermal management
- Understanding of low power microarchitecture techniques
- Understanding of high-performance techniques and trade-offs in a CPU microarchitecture
- Experience in C or C programming
- Experience using an interpretive language such as Perl or Python
As a CPU Microarchitect/RTL Engineer you will participate in the following: Micro-architecture development and specification - from early high-level architectural exploration through micro-architectural research and arriving at a detailed specification RTL ownership - development assessment and refi...
As a CPU Microarchitect/RTL Engineer you will participate in the following: Micro-architecture development and specification - from early high-level architectural exploration through micro-architectural research and arriving at a detailed specification RTL ownership - development assessment and refinement of RTL design to target power performance area and timing goals Verification - support the verification team in test bench development formal methods and simulation/emulation for formal verification Performance exploration and correlation - explore high-performance strategies and work with the performance verification team to verify that the RTL design meets targeted performance Design delivery - work with multi-functional engineering team to implement and verify physical design on the aspects of timing area reliability testability and power
- Minimum BS
- Experience with at least one of the following languages: Verilog or VHDL
- Expertise in one or more of the following areas: instruction fetch and decode branch prediction; instruction scheduling and register renaming out-of-order execution; integer and floating point execution; load/store execution; cache and memory subsystems; machine-learning algorithms and mapping to hardware; or power and thermal management
- Understanding of low power microarchitecture techniques
- Understanding of high-performance techniques and trade-offs in a CPU microarchitecture
- Experience in C or C programming
- Experience using an interpretive language such as Perl or Python
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