As a Wireless ASIC/FPGA Prototyping Design Engineer you will work in a team developing signal processing intensive design for wireless communication SoCs including:- ASIC prototyping from requirement to implementation and lab debug- FPGA synthesis define timing constraints timing closure- Maintain common design platform for ASIC as well as FPGA with considerations for memories I/O pads gated clocks and complex generated clocks- Bring-up debug and test FPGA/emulation model and collaterals in the lab- Support pre-Silicon and post-silicon validation and collaborate
- BS and 3 years of relevant experience
- Experience in FPGA flow
- Knowledge of digital design chip architecture and microarchitecture
- Experience in Scripting and modeling language experience (Shell C Python or Perl)
- Hand on experience in lab equipment hardware bring-up and debug in lab
- Strong background in computer architecture and wireless applications with expertise in one or more of the following areas: Bus fabric and peripherals APB/AHB/AXI USB I2C SPI and JTAG
- System debug architecture
- Wireless standards such as IEEE 802.11 and Bluetooth
- Familiar with AMDs flow including design entry in Verilog synthesis place and route timing constraints and timing closure
- Hands on experience with lab equipment such as JTAG oscilloscope logic analyzer and LitePoint
- Solid skill in problem solving FW/HW development
- Experience with emulation platform such as Palladium
- Excellent communication skills and self-motivation
- Ability to collaborate and drive production test/QA methodologies
As a Wireless ASIC/FPGA Prototyping Design Engineer you will work in a team developing signal processing intensive design for wireless communication SoCs including:- ASIC prototyping from requirement to implementation and lab debug- FPGA synthesis define timing constraints timing closure- Maintai...
As a Wireless ASIC/FPGA Prototyping Design Engineer you will work in a team developing signal processing intensive design for wireless communication SoCs including:- ASIC prototyping from requirement to implementation and lab debug- FPGA synthesis define timing constraints timing closure- Maintain common design platform for ASIC as well as FPGA with considerations for memories I/O pads gated clocks and complex generated clocks- Bring-up debug and test FPGA/emulation model and collaterals in the lab- Support pre-Silicon and post-silicon validation and collaborate
- BS and 3 years of relevant experience
- Experience in FPGA flow
- Knowledge of digital design chip architecture and microarchitecture
- Experience in Scripting and modeling language experience (Shell C Python or Perl)
- Hand on experience in lab equipment hardware bring-up and debug in lab
- Strong background in computer architecture and wireless applications with expertise in one or more of the following areas: Bus fabric and peripherals APB/AHB/AXI USB I2C SPI and JTAG
- System debug architecture
- Wireless standards such as IEEE 802.11 and Bluetooth
- Familiar with AMDs flow including design entry in Verilog synthesis place and route timing constraints and timing closure
- Hands on experience with lab equipment such as JTAG oscilloscope logic analyzer and LitePoint
- Solid skill in problem solving FW/HW development
- Experience with emulation platform such as Palladium
- Excellent communication skills and self-motivation
- Ability to collaborate and drive production test/QA methodologies
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