Timing & Synthesis Engineer
Timing & Synthesis Engineer
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Not Disclosed
Salary Not Disclosed
1 Vacancy
Job Description
- Bachelors degree and 3 years of relevant industry experience.
- Timing constraint (SDC) creation at partition and chip level.
- Logic synthesis execution (verilog RTL to netlist).
- Strong knowledge of the entire ASIC design process from RTL through synthesis static timing analysis and place & route.
- Expertise in STA tools and flow.
- UPF usage for power and voltage islands.
- Knowledge of timing corners operating modes process variation and signal integrity-related issues.
- Skilled in scripting languages (TCL PERL Python) both standalone and within EDA tools.
- Proficient in the closure of end-to-end logic equivalence (FV LEC) with functional ECOs in the mix.
- Familiarity with DFT approaches and constraints.
- Proficient with RTL Verilog/VHDL.
- Familiarity with digital top integration flows/methodology/checks.
Employment Type
Full Time
