PHY RTL Design Engineer
PHY RTL Design Engineer
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Salary Not Disclosed
1 Vacancy
Job Description
- Bachelors degree and 3 years of relevant industry experience.
- Understanding of DSP fundamentals.
- Digital Communications knowledge.
- Proficiency in RTL Design.
- Familiarity with UVM DV environment and AI based efficiency improvement flows.
- Strong fixed-point knowledge and extensive experience with bit-true cycle-accurate verifications.
- Understanding of Decoders - Viterbi LDPC Polar.
- Understanding of Filter design multi-radix implementation and compromises.
- Knowledgeable in modern design techniques and energy-efficient/low power logic design and power analysis.
- Familiarity with power estimation (vector-less and vector-based) modeling profiling and post-silicon power correlation.
- Solid understanding of wireless standards such as IEEE 802.11 802.15 Bluetooth or 3GPP is a plus.
- Background in computer architecture.
- Bus fabric especially APB/AHB/AXI.
- Power management with multiple power domains.
- Ability to work well in a team and be productive under ambitious schedules.
- Should exhibit excellent interpersonal skills and be self-motivated and well-organized.
- Experience with FPGA and/or emulation platform desired.
- Excellent communication skills both written and oral.
Employment Type
Full Time
