Join the team which delivers highly differentiated silicon into Blink and Ring battery powered devices. Our team works on state-of-the art SoCs in a vertically integrated team environment to deliver products our customers love. Drive early architectural and micro-architectural trade-offs to reduce time-to-revenue by shortening the time to revenue. Innovators will be delighted with our integrated verification/validation environment that is used to perform architectural modeling to post-silicon validation. The team works backwards from customer requirements to build super-low power energy efficient designs that include the latest in AI video processing low power communications and CMOS fabrication technology.
#ASICTW
Key job responsibilities
- Define architecture specifications based on requirements from product teams
- Create microarchitecture specifications suitable for being implemented by junior engineers
- Evaluate 3rd party IP blocks
- Estimate power performance and area for significant IPs early in design cycle
- Execute on design specifications to deliver high quality RTL
- Ensure quality by running and tracking results of front-end tools including: Synthesis Lint (RTL DFT UPF) Power Analysis and STA
- Take the lead and work with verification teams to define functional coverage
- Work with pre-silicon verification teams to assist in defining testplans/testbenches
- Work with post-silicon validation teams to define and execute on testplans
- Write high quality documents to guide and lead a scalable team
- Bachelors degree in Electrical Engineering or a related field
- Knowledge of UVM and Matlab
- Experience in communication theory OFDM MIMO Digital/Wireless Communication Systems or RF engineering
- Experience with current and upcoming RF standards in cellular (4G/5G) WiMAX 802.11ad microwave backhaul DVB-S2 / DVB-C or related broadband wireless standards
- Masters degree or Ph.D. degree in Electrical Engineering or related field
- Experience in RTL coding and debug as well as performance power area analysis and trade-offs
- Experience with modern ASIC/FPGA design and verification tools
- Experience with SOC bring-up and post-silicon validation
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