SeniorPrincipal ASIC RTL Design Engineer (SoCSubsystem)

Bangalore - India

Monthly Salary: Not Disclosed

Posted on: 30+ days ago

Vacancies: 1 Vacancy

Job Summary

Overview:

TekWissen is a global workforce management provider throughout India and many other countries in the world. The below client is a semiconductor and product engineering services company that provides silicon system and software design services including digital and analog design and project management

Position:Senior/Principal ASIC RTL Design Engineer (SoC/Subsystem)

Location: Bangalore

Work Type: Onsite
Job Type: Full time

Job Description:

Own end-to-end RTL design for complex SoC or large subsystem blocks from micro-architecture through tapeout and silicon bring-up.

Responsibilities:

Define micro-architecture from specs; write high-quality synthesizable SystemVerilog/Verilog RTL for SoC-level or large subsystems.
Own design bring-up block/subsystem integration and close on timing power and area with synthesis and PnR teams.
Drive design reviews close bugs and support silicon validation and post-silicon debug.
Collaborate with DV to define test plans assertions and coverage goals; support emulation/FPGA only as a secondary validation aid (not counted toward the 8 years).

Must-have qualifications:

8 years of hands-on ASIC RTL development experience (FPGA work does not count toward the 10 years).
Multiple production ASIC tapeouts owning significant SoC or subsystem functionality (e.g. interconnects coherency memory subsystem high-speed I/O security or power-management islands).
Strong SystemVerilog/Verilog RTL and micro-architecture skills including clock/reset design low-power techniques (UPF/retention/isolation) and AMBA/standard bus protocols (AXI/ACE/AHB/APB).
Proven collaboration with physical design on synthesis constraints timing closure DFT hooks and ECOs.
Proven silicon bring-up experience for owned blocks/subsystems.

Nice to Have:

Exposure to coherency protocols cache/memory controllers DDR/PCIe subsystems security/crypto blocks.
SVA for design-level assertions performance modeling or power/perf analysis skills.
Scripting for design productivity (Tcl/Python) used in service of hands-on RTL work.

Discounted / not counted experience:

FPGA design or prototyping experience does not count toward the minimum experience.
Lint/CDC-only roles integration-only roles without substantial new RTL creation or primarily tool-running roles will be discounted.
Pure management or architect-only with no recent hands-on RTL development will be discounted.

TekWissen Group is an equal opportunity employer supporting workforce diversity.

Overview: TekWissen is a global workforce management provider throughout India and many other countries in the world. The below client is a semiconductor and product engineering services company that provides silicon system and software design services including digital and analog design an...