In this highly visible role you will be: - Responsible for developing maintaining and enhancing our automation flows for constructing and modifying RTL for our SoCs across multiple design sites- Responsible for developing maintaining and enhancing our RTL Analysis Flows (RDC CDC Lint) application for our SoCs across multiple design sites- Responsible for writing Generative AI applications that enhance our RTL Construction and Analysis flows- Utilize your debugging experience to debug tool problems and collaborate with designers to help solve their problems- Work with EDA vendors to drive improvements and new methodologies
- Minimum requirement of Bachelors Degree 3 years of relevant industry experience
- Experience in programming languages such as Perl or Python
- Experience in Verilog/System Verilog
- Experience in Verific-based Verilog parsers and elaborator
- Demonstrated experience developing large-scale software system development from specification to deployment
- Demonstrated ability to take a spec create software to meet it develop the tests to validate the software document the software and support it with your customers
- Experience in Generative AI / LLM tools and applications
- Experience in RTL Analysis tools such as Reset-Domain-Crossing (RDC) and Clock-Domain-Crossing (CDC) methodologies
- Source control system management (Perforce Git) is a plus
- Excellent communication debug and root causing skills
In this highly visible role you will be: - Responsible for developing maintaining and enhancing our automation flows for constructing and modifying RTL for our SoCs across multiple design sites- Responsible for developing maintaining and enhancing our RTL Analysis Flows (RDC CDC Lint) application fo...
In this highly visible role you will be: - Responsible for developing maintaining and enhancing our automation flows for constructing and modifying RTL for our SoCs across multiple design sites- Responsible for developing maintaining and enhancing our RTL Analysis Flows (RDC CDC Lint) application for our SoCs across multiple design sites- Responsible for writing Generative AI applications that enhance our RTL Construction and Analysis flows- Utilize your debugging experience to debug tool problems and collaborate with designers to help solve their problems- Work with EDA vendors to drive improvements and new methodologies
- Minimum requirement of Bachelors Degree 3 years of relevant industry experience
- Experience in programming languages such as Perl or Python
- Experience in Verilog/System Verilog
- Experience in Verific-based Verilog parsers and elaborator
- Demonstrated experience developing large-scale software system development from specification to deployment
- Demonstrated ability to take a spec create software to meet it develop the tests to validate the software document the software and support it with your customers
- Experience in Generative AI / LLM tools and applications
- Experience in RTL Analysis tools such as Reset-Domain-Crossing (RDC) and Clock-Domain-Crossing (CDC) methodologies
- Source control system management (Perforce Git) is a plus
- Excellent communication debug and root causing skills
View more
View less