Senior Staff to Principal Engineer - ESD Design
Senior Staff to Principal Engineer - ESD Design
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Job Description
About Marvell
Marvells semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise cloud and AI automotive and carrier architectures our innovative technology is enabling new possibilities.
At Marvell you can affect the arc of individual lives lift the trajectory of entire industries and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation above and beyond fleeting trends Marvell is a place to thrive learn and lead.
Your Team Your Impact
As a Digital IC Design Senior Staff/Principal Engineer with Marvell youll be a member of the Central Engineering business group. If you picture Marvell as a wheel Central Engineering is the center hub providing IP to be used by all the other spokes on that wheel including Automotive Storage Security and Networking. Youll be playing a crucial role in establishing ESD requirements and validating ESD solutions for Foundational IP SerDes IP and SOCs during the ESD qualification process. You will work closely with the Physical Design Electrical Engineering and SOC (System on Chip) teams to provide support from the initial design phase through failure analysis issue root cause determination and the development of corrective actions. Being part of interface design team you will have opportunities for the development of IO circuit to customer specifications including the generation and delivery of final EDA views for the IP. Typical circuits to be developed include biasing blocks over-voltage/over-current protection circuits regulators amplifiers switches and a range of closed loop feedback circuits.This team hires some of the biggest problem solvers in Silicon and has a huge impact on the work done at Marvell. The customers served by this team are often other chip companies and big tech companies familiar names to all candidates.
What You Can Expect
- Provide co-design support with both ESD simulations of circuits to maximize both performance and ESD protection robustness.
- Perform ESD design reviews and provide the required technical guidance for analog foundational IP SOCs and qualification test chips for multiple technology nodes ranging from 45nm to 2nm across major foundry platforms.
- Validate and characterize ESD circuits using ICV PERC Calibre PERC TLP-based SPICE simulation and any other industry methods and tools.
- Design enablement of ESD protection schemes for analog design like SerDes. This will include understanding ESD protection design latch-up transient latch-up as well as ESD design verification and EDA tools.
- Continue the development of best practices for ESD in the technologies being supported.
- Development and support of EDA tools for ESD design checking.
- Development of circuits like Driver Receiver Overvoltage protection circuits Fail safe I/O Bandgap and Voltage Regulators.
What Were Looking For
- Bachelors or Masters degree and/or PhD in Electrical/Electronic Engineering Microelectronics or related fields and 8-15 years of related professional experience.
- Expertise in custom circuit design handling layout effect in advanced FinFET process design rules process variability and circuit reliability issues that affect power speed area and yield.
- Advanced knowledge of on-chip ESD protection circuit design
- Advanced knowledge of CAD design tools such as Cadence and SPICE
- Applicant should have sufficient design experience to be able to effectively review designs and communicate ESD design deficiencies to product design engineering.
- Advanced knowledge of ESD relevant device physics such as snapback and other high-level injection phenomenon/device operations
- Fully familiar with industry ESD test standards and latest developments.
- Experience with verifying ESD analysis for IP and SoC level using industry standard tools and methodologies.
- Exposure and experience with the Custom ESD PERC code development will have added advantage to this role.
- Experience with simulation skills using cadence including PEX Monte Carlo and Corner analysis.
- Derive design specifications from customer requirement.
- Requires effective communication between multiple sites and ability to work with multiple groups.
Additional Compensation and Benefit Elements
With competitive compensation and great benefits you will enjoy our workstyle within an environment of shared collaboration transparency and inclusivity. Were dedicated to giving our people the tools and resources they need to succeed in doing work that matters and to grow and develop with us. For additional information on what its like to work at Marvell visit our Careers page.
All qualified applicants will receive consideration for employment without regard to race color religion sex national origin sexual orientation gender identity disability or protected veteran status.
#LI-CP1Required Experience:
Staff IC
Employment Type
Full-Time
