Logic Back-End Synthesis APR Structural Design Engineer
Logic Back-End Synthesis APR Structural Design Engineer
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1 Vacancy
Job Description
-Responsible for RTL-to-GDS synth/apr large logic partition of 3D NAND design -Drive design flow improvement from existing DC/ICC2 to Fuse-Compiler R2G -MS with 4 years or BS with 7 years of experience in BE design
In this role you will drive advanced RTL-to-GDS process of the several large logic controller partitions of 3D NAND chip design. This involves synthesis place-and-route timing closure post-r2g to schematic conversion on Virtuoso and layout DRC. Youll also help drive the flow improvement from the existing DC/ICC2 flow to the more advanced Fusion Compiler flow
Qualifications :
-MS with 4 years or BS with 7 years of experience in BE design
-Expert knowledge of System-Verilog
-Expert in Synthesis Place & Route PrimeTime and DRC
-Expert in DC/ICC2 and Fusion-Compiler tool set/env
-Strong knowledge of design PDK esp. stdcell
-Strong background in physical layout design and layout verification
-Solid Virtuoso schematic/layout environment
-Desired knowledge of NVM NAND algo controller
Additional Information :
The compensation range for this role is $119130 - $178690. Actual compensation is influenced by a variety of factors including but not limited to skills experience qualifications and geographic location.
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Remote Work :
No
Employment Type :
Full-time
Employment Type
Full-time
