Senior Engineer, Analog Layout
Senior Engineer, Analog Layout
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Job Description
About Marvell
Marvells semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise cloud and AI automotive and carrier architectures our innovative technology is enabling new possibilities.
At Marvell you can affect the arc of individual lives lift the trajectory of entire industries and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation above and beyond fleeting trends Marvell is a place to thrive learn and lead.
Your Team Your Impact
We are seeking highly skilled and motivated Senior Analog Layout Engineers to join our dynamic this role you will contribute the development of General Purpose IOs (GPIO) and IO ESD solutions across different process nodes addressing the needs of hyperscale datacom centers automotive and other advanced applications. You will also have the exciting opportunity to learn and work with ESD experts; and help with reviewing some of the most worlds advanced SoCs in the latest process nodes. The candidate should have good layout experience and have strong willingness to learn.What You Can Expect
- Physical layout and verification of high speed I/O circuits General Purpose I/Os ESD structures with the latest process nodes using Cadence tools.
- Work closely with ESD leads to support worldwide Marvell in IP/SoC ESD/LUP DRC/ERC reviews (training will be provided).
- Work closely with CAD team to implement ESD/LUP rules for different process nodes.
- Help with releasing I/O IP libraries.
- Help implement project specific guidelines and conduct peer-to-peer layout quality checks.
- Contribute to overall team through tool testing script development flow documentation training etc.
- Keep abreast with technology tool developments and bring new ideas to the team.
What Were Looking For
- Bachelors or Masters degree in Computer Science Electrical Engineering or related fields and at least 3 years of related professional experience.
- Good understanding of semiconductor and circuit design.
- Good understanding of analog mixed-signal layout best practices.
- Have high level proficiency/knowledge of Synopsys or CADENCE layout entry tools.
- FinFet layout experience is a plus.
- ESD / latch-up knowledge is a plus.
- Have high level proficiency in the interpretation of CALIBRE DRC ERC LVS etc. reports.
- Scripting skills in PERL TCL or SKILL are considered a plus but not required.
- Independent with strong analytical skills creative thinking and self-motivated.
- Excellent communication skills and able to work with cross-functional teams.
- Ability to thrive in a fast-paced global environment.
Additional Compensation and Benefit Elements
With competitive compensation and great benefits you will enjoy our workstyle within an environment of shared collaboration transparency and inclusivity. Were dedicated to giving our people the tools and resources they need to succeed in doing work that matters and to grow and develop with us. For additional information on what its like to work at Marvell visit our Careers page.
All qualified applicants will receive consideration for employment without regard to race color religion sex national origin sexual orientation gender identity disability or protected veteran status.
#LI-UN1Required Experience:
Senior IC
Employment Type
Full Time
