Computer Science Internship: Benchmarking Open-Source Alternatives to MATLAB for HDL Code Generation in Model-Based Design

Introduction

This internship investigates the feasibility of using open-source alternatives for model-based design and HDL code generation. The intern will develop a reference algorithm in MATLAB/Simulink GNU Octave Scilab and Python and use available toolchains (e.g. HDL Coder Octave HDL packages Scilab-to-HDL tools MyHDL) to generate HDL code from each environment. The goal is to benchmark the generated HDL in terms of performance resource usage and code quality and assess the viability of these tools as part of a more diversified and sustainable development ecosystem.

Your assignment

During this internship you will:

• Define a representative reference design (e.g. a digital filter PID controller or signal processing block).
• Implement the design in:
  • MATLAB/Simulink (using HDL Coder)
  • GNU Octave (with HDL packages)
  • Scilab (with Scicos and HDL export tools)
  • Python (using MyHDL or similar frameworks)
• Generate HDL code from each implementation.
• Simulate and synthesize the HDL using a common FPGA toolchain (e.g. Vivado Quartus or open-source tools like Yosys).
• Benchmark the results based on:
  • Logic resource usage
  • Timing performance
  • Code readability and maintainability
  • Toolchain usability and maturity

• Document the workflow challenges and findings.
• Present a comparative analysis and recommendations for future toolchain diversification.
• Create a poster for a possible conference.

Learning Objectives:

• Understand the workflow of model-based design and HDL code generation.
• Gain hands-on experience with MATLAB Octave Scilab and Python-based HDL tools.
• Learn benchmarking techniques for comparing HDL implementations.
• Contribute to strategic tooling decisions by evaluating open-source alternatives.

This is a master graduation (thesis) project for 3-5 days a week with a duration of 3-6 months. The start date of this internship is as soon as possible.

Your profile

To be a fit for this internship you:

• Have a curious analytical and methodical mindset.
• Have strong interest in HDL Programming (VHDL/Verilog) Model-Based Design(MATLAB Simulink) Digital Signal Processing (DSP) and Control Systems.
• Preferably have familiarity with FPGA architectures and programming.
• Have the willingness to explore new tools with a problem-solving mindset.

Other requirements you need to meet

• You are enrolled at an educational institutefor the entire duration of the internship;
• You need to be located in the Netherlands to be perform your case you re currently living/studying outside of the Netherlands your CV/motivation letter includes the willingness to relocate.
• If you are a non-EU citizen studying in the Netherlands your university is willing to sign the documents relevant for doing an internship (i.e. Nuffic agreement).

This position requires access to controlled technology as defined in the United States Export Administration Regulations (15 C.F.R. 730 et seq.). Qualified candidates must be legally authorized to access such controlled technology prior to beginning work. Business demands may require ASML to proceed with candidates who are immediately eligible to access controlled technology.

Diversity and inclusion

ASML is an Equal Opportunity Employer that values and respects the importance of a diverse and inclusive workforce. It is the policy of the company to recruit hire train and promote persons in all job titles without regard to race color religion sex age national origin veteran status disability sexual orientation or gender identity. We recognize that diversity and inclusion is a driving force in the success of our company.

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