PSV SOC Validation Engineer
PSV SOC Validation Engineer
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Salary Not Disclosed
1 Vacancy
Job Description
Location: San Jose
- Lead the development and execution of bring-up and silicon validation test plans for the SoC.
- Perform validation of SoC peripherals including LPDDRx PCIe I2C and qSPI.
- Manage and oversee all phases of the validation lifecycle from initial bring-up to production release.
- Collaborate closely with cross-functional hardware and software teams to design and implement effective validation and characterization strategies.
- Develop and integrate software-based test applications for stress testing and SLT screening working with software teams to assess system performance and hardware/software interactions under diverse conditions.
- Drive continuous improvement initiatives in validation and productization processes to boost efficiency and ensure high-quality deliverables.
- 10 years of SOC validation experience
- Strong understanding of digital design circuit design and analysis computer architecture and SOC architecture.
- Knowledge of DDR training and memory system operation a plus
- Hands-on experience with silicon bring-up debugging and characterization of SoC-level IPs (e.g. PCIe Gen 4/5 LPDDR4/5 PLL/DLL NOR Flash SPI I2C RISC-V processors) with familiarity in memory and I/O interfaces.
- Proficiency in programming/scripting (C/C Perl Ruby Python) for automation test
- Experience with Lauterbach Debugger for RISC-V and lab equipment (oscilloscopes BERT power supplies logic analyzers).
- Solid foundation in digital design microarchitecture timing power noise control systems and HW/SW interaction including firmware.
- scripting and GUI development. Knowledge of signal and power integrity is a plus
Employment Type
Full-time
