GPU Physical Design Engineer, STA/Timing
GPU Physical Design Engineer, STA/Timing
Posted on :
04-08-2025
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1 Vacancy
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Job Description
In this role you will: - Lead different STA activities at the same time by working with functional collaborators.- Identify dependencies and roadblocks for different STA items very early on and ensure a smooth execution of timing closure.- Participate in analysis leading to the definition of next generation products.- Interact with RTL architecture teams to understand physical design constraints related to timing and be the central point of contact to provide these to backend design flows.- Work with Synthesis and Physical Design teams to implement the best design optimized for power performance and timing.- Setting up all DFT modes and making sure all test features are properly timed.- Assemble the top level design for STA ensuring accurate analysis by reviewing all the logs and reports.- Create and maintain scripts and automation to ensure high quality STA reports and work with other teams for timing closure.- Run ECO flows on the design and responsible for close timing.- Drive and support tapeout activities by running a full suite of signoff checks to ensure a high quality silicon for manufacture.- Work with CAD and Vendors to constantly improve the flow and bring in groundbreaking features to the analysis flows.- Work with post silicon teams and product engineering for silicon debug activities.
- Bachelors degree in Computer Science or Computer Engineering 10 years relevant experience.
- Experience in STA and leading timing closure efforts.
- Experience with STA concepts such as cross-talk OCV noise etc.
- Experience with scripting languages like TCL Python Perl shell scripting etc.
- Experience working with EDA tools and exposure to their APIs.
- Masters degree preferred.
- A good track record for driving timing closure experience.
- Able to constraint the design for different modes of timing closure by working with IP RTL DFT teams.
- Able to independently work with other functional teams and make the right decisions to help timing closure.
- Experience working with post silicon debug and timing correlation.
- Able to contribute for improving PPA of the product.
- Experience in setting up freq. targets for future generations experience working with new process technology enablement.
Employment Type
Full Time
Key Skills
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