CAD Engineer - Timing for Gate-Level Flows & Methodologies
CAD Engineer - Timing for Gate-Level Flows & Methodologies
Posted on :
02-08-2025
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1 Vacancy
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Job Description
As a member of our STA CAD team you will: Develop maintain and enhance existing gate-level STA flows for Apple silicon designs Work with design teams to understand and debug issues related to constraints flow scripts and timing closure Facilitate and drive STA methodology changes to improve overall STA flows as it relates to efficiency/productivity and silicon timing correlation Develop and maintain scripts and methods for timing analysis and power reduction Develop and support methodologies tools and flows used in the verification of timing constraints drive best practices across design teams Analysis of timing paths to identify key issues including post-silicon timing debug Work closely with EDA vendors to develop and incorporate new capabilities to solve technical problems
- Minimum requirement of BS and 10 years of relevant industry experience.
- Expert power user of static timing analysis tools and flows
- Advanced programming skills with Python and Tcl or other high level programming languages
- Proven track record of development and deployment of complex CAD flows and automation
- Familiar with STA of large high-performance SoC designs in deep sub-micron technologies
- Deep understanding of noise cross-talk variation margins and timing models
- Knowledge of timing/SDC constraints hands on experience in creation and validation of constraints
- Excellent communicator who can accurately assess and describe issues to management as well as follow solutions through to completion
Employment Type
Full Time
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