SerDes Lead Circuit Design Engineer
SerDes Lead Circuit Design Engineer
Posted on :
02-08-2025
Employer Active
1 Vacancy
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Monthly Salary
USD 257400 - 386300
Vacancy
1 Vacancy
Posted on :
02-08-2025
Job Description
You will work on the development of high-performance and high-speed AMS circuits used in SerDes PHY including evaluation of different circuit topologies for specific product requirements (e.g. Rx CDR Tx bias generator high-speed clock generation and low-jitter distribution phase interpolator DLL VCO LDO) with best in class power performance and area (PPA). You will be leading discussions with cross-functional teams (e.g. architecture SIPI packaging board design DFT ESD) to create and drive block-level specifications mixed-signal implementations and behavioral modeling. You will closely work with SOC teams to deliver IP views and make sure they meet the quality standards. While developing these complex IPs on regular basis you will interact with your peers/management to communicate progress discuss new ideas and drive new implementations/concepts making it a rewarding and growth-oriented work environment.
- BSEE with 20 years of proven experience.
- The ideal candidate should have deep understanding of analog mixed-signal design with experience in high-speed serial links.
- Solid understanding and experience of designing analog mixed signal circuit blocks including Bandgap biasing circuits LDO regulators amplifiers comparators switched-cap circuits ADCs DACs Oscillators Filters
- Solid understanding of analog mixed-signal concepts like mismatch mitigation linearity stability low-power and low-noise techniques
- Solid understanding and experience with digitally assisted analog design concepts (e.g. background calibrations LMS based adaptive loops)
- Proven track record of working with system and architecture teams to drive block-level and IP requirements
- Proven track record of working with large teams and guiding junior engineers
- Experience with high speed digital circuits (e.g. serializer deserializer counters dividers etc.) with solid understanding of digital design concepts
- Experience and solid understanding of Tx/Rx equalization techniques and circuits (e.g. CTLE DFE de-emphasis) for 64-100 Gbps NRZ and PAM applications
- Experience with EQ adaptation methods and circuit interactions to improve PPA
- Solid understanding of CDR architectures and implementations
- Experience in Analog Mixed Signal circuit modeling and performance evaluation (e.g. SystemVerilog Matlab Python VerilogAMS)
- Hands-on experience to drive lab testing debug and data analysis
- Hands-on experience in advanced CMOS technologies design with FinFet technology
- Hands-on experience with AMS IC development from definition to high-volume production including layout supervision bench evaluation correlation and characterization
- Experience in the following areas is a plus
- Concepts of timing closure and related industry tools (e.g. Nanotime Primetime)
- Concepts of IP delivery and quality checks
- Knowledge of common high-speed SerDes protocols (e.g. PCIe USB DP MPHY) is highly desired
- Skills in scripting and automation to enhance efficiency are highly desirable
Employment Type
Full Time
Key Skills
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