Design Verification Engineer
Design Verification Engineer
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Salary Not Disclosed
1 Vacancy
Job Description
We are looking for a skilled Design Verification Engineer with experience in IOMMU architecture and ISO 26262 compliance to join our semiconductor/automotive verification team. You will be responsible for developing implementing and executing verification environments for complex IPs/subsystems with a focus on functional safety and memory management.
Develop and execute UVM-based testbenches for verifying IOMMU IP/SoC components.
Analyze architecture and functional specifications to define verification plans including corner-case and safety scenarios.
Drive functional coverage and code coverage closure.
Validate integration of IOMMU with other system components (e.g. MMU DMA peripherals).
Ensure compliance with ISO 26262 ASIL levels by integrating fault injection error handling and safety verification.
Work with RTL designers safety engineers and SoC architects to identify and resolve issues.
Participate in safety analysis (FMEA FMEDA) and verification traceability.
Develop automation scripts for test execution and regression using Python/Perl/Shell.
Deliver high-quality testbenches test cases and documentation in accordance with quality and safety standards.
Strong experience with SystemVerilog/UVM and SoC/IP level verification.
Deep understanding of IOMMU design memory protection translation lookaside buffers (TLBs) and related protocols (AXI AHB etc.).
Hands-on knowledge of ISO 26262 standard especially safety verification and fault injection.
Familiarity with functional safety flows including FMEDA DFMEA and safety requirements traceability.
Solid debugging skills using waveform tools (e.g. DVE Verdi SimVision).
Proficiency with simulation tools (VCS Questa Incisive etc.).
Exposure to formal verification assertions (SVA) and coverage-driven verification.
Employment Type
Full-time
