Principal ASIC Design Engineer

About Marvell

Marvells semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise cloud and AI and carrier architectures our innovative technology is enabling new possibilities.

At Marvell you can affect the arc of individual lives lift the trajectory of entire industries and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation above and beyond fleeting trends Marvell is a place to thrive learn and lead.

This is an existing vacancy.

Your Team Your Impact

What You Can Expect

• Participate in the micro-architecture definition of various SubSystems and/or the chip
• Write specifications and micro-architecture of the design
• Implement designs using low-power RTL coding techniques
• Collaborate with the verification team on the verification test plan coverage analysis and full-chip simulation plus debug
• Work with the physical design team in aiding the implementation of the functional blocks
• Interact with the project lead to scope tasks
• Work with multiple design centers and design groups on the development of the projects
• Support the post silicon team to bring up silicon in the lab
• Work with the software team and in some cases the customer to ensure product meets customer use cases

What Were Looking For

Bachelors degree in Computer Science Electrical Engineering or related fields and 10 years of related professional experience. Or Masters degree in Computer Science Electrical Engineering or related fields with 8 years of experience.

To be successful in this role you will need to be:

• Fluent in System Verilog RTL coding techniques.

• Familiar with modern SoC architectures and various interface technologies such as AXI HBM LPDDR/DDR Ethernet PCIe D2D.

• Experience in micro-architecture of complex custom/ASIC products focusing in one or more of the following areas: NPU AI accelerators embedded processors DSP graphics and general purpose microprocessors.

• RTL design experience synthesis static-timing closure formal verification gate-level simulations and block-level functional verification.

• Experience in implementation/timing closure for high speed design.

• Hands-on experience for all aspects of chip-development process with proficiency in front-end design tools and methodologies is a plus.

• Experience in memory interface design (HBM LPDDR/DDR) is a plus.

• Knowledge of scripting languages such as Python Perl Tcl and UNIX shell is desirable.

Expected Base Pay Range (CAD)

Additional Compensation and Benefit Elements

With competitive compensation and great benefits you will enjoy our workstyle within an environment of shared collaboration transparency and inclusivity. Were dedicated to giving our people the tools and resources they need to succeed in doing work that matters and to grow and develop with us. For additional information on what its like to work at Marvell visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race color religion sex national origin sexual orientation gender identity disability or protected veteran status.

Interview Integrity

To support fair and authentic hiring practices candidates are not permitted to use AI tools (such as transcription apps real-time answer generators like ChatGPT or Copilot or automated note-taking bots) during interviews.

These tools must not be used to record assist with or enhance responses in any way. Our interviews are designed to evaluate your individual experience thought process and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations including the Export Administration Regulations (EAR). As such applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens lawful permanent residents or protected individuals as defined by 8 U.S.C. 1324b(a)(3) all applicants may be subject to an export license review process prior to employment.

Marvell may employ artificial intelligence technologies to assist in the evaluation of job applications. All application reviews include meaningful human involvement and no hiring decisions are made solely on the basis of automated processing.