Sr Staff Physical Design Engineer - Static Timing Analysis
Sr Staff Physical Design Engineer - Static Timing Analysis
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1 Vacancy
Job Description
About Marvell
Marvells semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise cloud and AI automotive and carrier architectures our innovative technology is enabling new possibilities.
At Marvell you can affect the arc of individual lives lift the trajectory of entire industries and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation above and beyond fleeting trends Marvell is a place to thrive learn and lead.
Your Team Your Impact
The Design Center Engineering Physical Design team at Marvell in Westborough MA is seeking a Sr. Staff Static Timing Analysis (STA) Engineer to contribute to a wide range of innovative projectsfrom artificial intelligence and machine learning to advanced wired and wireless infrastructureusing the latest technology nodes.Our team leverages cutting-edge EDA tools to solve complex challenges and ensure our designs meet critical performance power and area (PPA) goals. This role involves close collaboration with Physical Design Design for Test (DFT) and other cross-functional teams across both local and global sites.
If youre looking to apply your STA expertise in a dynamic and forward-thinking environment this is a great opportunity to explore.
What You Can Expect
This position is a full-time in-office role located in Westborough MA.
Perform timing analysis and closure on complex partitions.
Develop and implement timing closure and logical ECOs.
Interface with the RTL design team to drive design modifications to resolve congestion and timing issues.
Work with the global timing team in debugging/resolving any block level timing issues seen at full chip.
Experienced with the balancing the trade-offs of Performance Power and Area.
Maintain enhance and support Marvells timing and/or power flows.
Test and maintain chip end-to-end flows with specific focus on timing and/or power.
Interact with tool vendors to drive tool fixes and improvements in support of on-going and planned CAD activities.
Perform tool evaluations of new vendor tools and functions.
What Were Looking For
Bachelors degree in Computer Science Electrical Engineering or related fields and 3-5 years of related professional experience. Masters degree and/or PhD in Computer Science Electrical Engineering or related fields with 2-3 years of experience.
Practical experience in Timing Analysis and Closure on multiple ASICs/SOCs at a partition/sub-system or full-chip level.
Experience working in the latest technology nodes and knowlegdable about advanced timing concepts such as SI CDC LVF POCV and MIS.
Experience with industry standard STA tools such as Primetime and Tweaker.
Exposure to Verilog/VHDL along with general knowledge of digital logic and architecture.
Proficiency at running partition/sub-system and/or fullchip level timing signoff
Proficiency with UNIX and shell based scripting.
Knowledge and Experience in both TCL or Python languages.
Experienced with the balancing the trade-offs of Performance Power and Area.
General knowledge of Synthesis and Physical Design and their impact on timing.
Diligent detail-oriented and able to handle assignments with minimal supervision.
Good communication skills self-driven and a good team player.
Expected Base Pay Range (USD)
139800 - 206900 $ per annumThe successful candidates starting base pay will be determined based on job-related skills experience qualifications work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
At Marvell we offer a total compensation package with a base bonus and and financial wellbeing are part of the package. That means flexible time off 401k plus a year-end shutdown floating holidays paid time off to volunteer. Have a question about our benefits packages - health or financial Ask your recruiter during the interview process.All qualified applicants will receive consideration for employment without regard to race color religion sex national origin sexual orientation gender identity disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at .
#LI-VM1Required Experience:
Staff IC
Employment Type
Full-Time
