Design Verification Lead Engineer
Design Verification Lead Engineer
Posted on :
14-07-2025
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1 Vacancy
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Job Description
Job Title : Design Verification Lead Engineer
Job location: Austin TX
Job Duration: 3 Months Contract to Hire
Job location: Austin TX
Job Duration: 3 Months Contract to Hire
Job Description:
- 10 years of experience in pre-silicon design verification
- Proficiency in C-shell scripting Verilog-HDL & System Verilog.
- Strong knowledge in SV Assertions UVM/OVM and functional code coverage.
- SOC Verification experience using ARM Cortex Microcontroller is required.
- Experience with advanced peripheral bus Verification IPs such as GPIO UART SPI SW JTAG and I2C.
- Proficient with Cadence tools such as NCVerilog NCSIM Simvision. Experience with linting tools (i.e Spyglass) will be helpful.
- Exposure to SDF annotated simulations with good understanding of parasitic delays and timings is required.
- Exposure to FPGA programming and FPGA tools will be helpful.
- Independent self-motivated with good analytical & communication skills.
- Ability to Lead fellow CWF and be responsible for delivery
- Good communication is a must have
- Proficient leading areas within SOC Verification
- Familiar with SOC Environment methodology and flows.
- Ability to debug and also coach fellow team member to debug effectively
- ARM Processor and CHI working experience
- PCIE or DDR hands on experience
- SOC Verification Experience on ARM Ecosystem
- PCIE Experience and alsoPCIE-VIP usage experience
- GLS working experience
- Proficient in C/System Verilog and UVM
- Working knowledge of GIT
- Soft skill -Good Communication and willingness to learn
Skills:
- UVM/System Verilog (Preference: 5)
- Python (Preference: 3)
- Synopsys/Cadence EDA Verification Tools (Preference: 4
Employment Type
Full-time
Key Skills
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