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We are seeking an experienced trainer to deliver hands-on sessions on Synopsys Fusion Compiler focusing on RTL-to-GDSII digital design flow. The ideal candidate should have a strong background in ASIC/SoC design physical implementation and optimization techniques using industry-standard EDA tools.
Deliver structured training on RTL synthesis floorplanning placement clock tree synthesis routing and timing closure using Fusion Compiler
Guide learners through GUI and TCL-based flows MCMM setup and power intent implementation
Provide real-world examples and lab exercises for QoR optimization (area power timing)
Support participants with tool usage debugging and design best practices
Customize content for design engineers physical design teams and corporate clients
Proficiency in Fusion Compiler Design Compiler and PrimeTime
Strong understanding of ASIC design flow standard cell libraries and physical design constraints
Experience with TCL scripting floorplanning and timing analysis
Familiarity with MCMM low-power design and DFT-aware synthesis
Excellent communication and instructional delivery skills
Full Time