Senior Engineer, Physical Design
Senior Engineer, Physical Design
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Job Description
About Marvell
Marvells semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise cloud and AI automotive and carrier architectures our innovative technology is enabling new possibilities.
At Marvell you can affect the arc of individual lives lift the trajectory of entire industries and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation above and beyond fleeting trends Marvell is a place to thrive learn and lead.
Your Team Your Impact
Built on decades of expertise and execution Marvells custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data infrastructure intellectual property (IP) and a wide array of flexible business models. In this unique role youll have the opportunity to work on both the physical design and methodology for future designs of our next-generation high-performance processor chips in a leading-edge CMOS process technology targeted at server 5G/6G and networking applications.What You Can Expect
In this role based in Bucharest Romania you will work with a global team on both the physical design of complex chips as well as the methodology to enable an efficient and robust design process. Every day youll be working hands-on to triage workflows whether youre running RTL code through synthesis and place and route (PnR) tools to create the physical view of the chip analyzing performance by running timing analysis verifying a robust power grid by performing EMIR analysis etc. There are many sign-off checks that need to happen to verify that the database is ready to move on to the next level and its your responsibility to review completed runs for errors or create optimizations from successful runs.
What Were Looking For
To be successful in this role you must:
Bachelors Masters or PhD degree in Electrical Engineering Computer Engineering or a related field.
3 years of experience in physical design with a focus on block-level PNR for advanced CMOS process nodes (e.g. 7nm 5nm or below).
Working experience with industry-standard EDA tools for physical design including Cadence Genus and Innovus and Synopsys IC Compiler and Fusion Compiler.
Working knowledge of static timing analysis tools such as Tempus or PrimeTime and EM/IR-Drop/Crosstalk analysis tools like Voltus or PrimeRail is advantageous.
Working knowledge of physical verification and formal verification tools (e.g. Calibre LEC Formality) is advantageous.
Enjoy learning by doing the work and having access to guides and a mentor.
Be willing to raise your hand and volunteer for learning opportunities you may not have experienced before.
Additional Compensation and Benefit Elements
With competitive compensation and great benefits you will enjoy our workstyle within an environment of shared collaboration transparency and inclusivity. Were dedicated to giving our people the tools and resources they need to succeed in doing work that matters and to grow and develop with us. For additional information on what its like to work at Marvell visit our Careers page.
All qualified applicants will receive consideration for employment without regard to race color religion sex national origin sexual orientation gender identity disability or protected veteran status.
#LI-AB3Required Experience:
Senior IC
Employment Type
Full-Time
