RTL Design Engineer (ASIC, IP Design)
RTL Design Engineer (ASIC, IP Design)
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Job Description
About Marvell
Marvells semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise cloud and AI automotive and carrier architectures our innovative technology is enabling new possibilities.
At Marvell you can affect the arc of individual lives lift the trajectory of entire industries and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation above and beyond fleeting trends Marvell is a place to thrive learn and lead.
Your Team Your Impact
The Switch Business Unit in Marvell designs and develops the next generation datacenter and enterprise System-On-Chip switch processors on leading edge process technology. We develop the architecture collaborate on IP development create the physical design develop switching solutions and work with the worlds leading data center and enterprise companies to bring next generation networking to reality.What You Can Expect
You will completely own the egress processor IP design Including:
Closely working with architecture team to understand the feature enhancement needs.
Implement a specification using RTL coding techniques.
Ensuring all quality criteria are met.
Must be familiar with Digital IC design methodologies understand all stages of ASIC design flows and experienced with state-of-the-art design tools.
Work with the physical design teams for synthesis and timing signoff.
Work with the Verification team on pre-silicon verification tasks such as reviewing the verification test plan coverage analysis and full-chip simulation and related debug.
Strong Knowledge of HDL and experience in Verilog coding Perform RTL coding
Strong Knowledge of logic synthesis and timing analysis.
Networking knowledge is a plus.
What Were Looking For
Masters degree and/or PhD/Bachelors degree in Computer Science Electrical Engineering or related fields with 4 to 20 years of relevant industry experience.
Experience with digital design microarchitecture development is a must.
Design/RTL experience in Verilog or SV is a must.
Experience with logic synthesis synthesis constraint development and backend flow and static timing analysis.
Knowledge of scripting languages such as PERL Python
Ethernet protocols (IEEE 802.3 802.1Q 802.1D Routing protocols) preferred.
L2 / L3 / L4 Ethernet protocol knowledge
Encryption / Authentication algorithms.
Precision Time Protocol (PTP IEEE-1588)
Knowledge of GIT version control system
Good learning problem solving interpersonal and communication skills.
Ability to be a part of a team working in cooperation.
Self-motivated team player able to thrive in a fast-paced engineering environment.
Additional Compensation and Benefit Elements
With competitive compensation and great benefits you will enjoy our workstyle within an environment of shared collaboration transparency and inclusivity. Were dedicated to giving our people the tools and resources they need to succeed in doing work that matters and to grow and develop with us. For additional information on what its like to work at Marvell visit our Careers page.
All qualified applicants will receive consideration for employment without regard to race color religion sex national origin sexual orientation gender identity disability or protected veteran status.
#LI-RS1Employment Type
Full-Time
