Analog/MixedSignal Verification Engineer Remote / work from home US Citizen or US Permanent Resident Fulltime/employee Benefits 401k Stock Options
You will work on a small talented team responsible for developing new verification techniques to verify stateoftheart circuits and systems ensuring their accuracy and reliability prior to tapeouts. You will have the opportunity to contribute to all areas of AMS verification including behavioral modeling simulation and mixedsignal integration. Projects range from verifying highspeed lownoise analog circuits to ensuring the correctness of complex directRF digital beamforming and secure hardware systems.
Responsibilities: Collaborate with design teams to identify verification gaps and propose coveragedriven solutions. Contribute to postsilicon validation debugging and characterization efforts to ensure correlation with presilicon verification. Create behavioral models of analog and RF components in SystemVerilog VerilogA VerilogAMS or other relevant modeling languages. Define testbenches and validation plans to ensure seamless integration between analog and digital subsystems. Develop and execute AMS verification methodologies for highperformance analog mixedsignal and RF circuits including DACs/ADCs PLLs LNAs and VGAs. Perform functional and mixedsignal verification using industrystandard AMS simulation tools. Stay up to date with advancements in AMS verification methodologies tools and semiconductor process technologies.
Skills & Experience: Experience in developing advanced verification flows from the ground up Experience with analog mixedsignal and RF circuit verification including behavioral modeling simulation and validation Expertise in industrystandard AMS verification tools such as: Cadence Virtuoso Spectre and ADEXL Realnumber emulation on the Cadence Palladium or Synopsys ZeBu platforms VCS Xcelium PhD research experience or BSEE/MSEE with 5 years of relevant experience Proficiency in VerilogA VerilogAMS and SystemVerilog real number modeling for mixedsignal verification
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