Own the implementation of block level subcomponents and their physical integration into the
top level of a systemonachip (SoC). The design cycle will start with synthesis of various
hierarchies to translate a High Level Description Language view of the functionality (Verilog
RTL) into a Gate Level Description (Verilog netlist). Take the netlist through the various steps
of a Place and Route flow (PnR) to produce manufacturable database (GDS) that meet all the
requirements of performance power and area specifications of the final product. Optimize floor
plans to integrate intellectual property cores and subsystems from internal groups and external
partners to achieve the smallest footprint area while satisfying all electrical integrity
requirements. Generate physical and timing constraints for subblock implementation. Design
implement and analyze high frequency clock distribution networks at the top and block level to
enable communication between synchronous elements. Design implement and analyze high
performance interfaces between subsystems of the SoC for high speed communication. Analyze
and close timing by implementing design changes and finetuning of critical timing paths to
ensure the part operates at the target frequency. Run physical verification and implement fixes
to satisfy the design rules established by the chip foundry. Contribute to the automation of the
PnR flow by writing code in industry standard scripting languages to add customization and
collect metrics.