ASIC Physical Design Engineer (analog upper tariff / PC05, f/m/div.)
ASIC Physical Design Engineer (analog upper tariff / PC05, f/m/div.)
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Job Description
In our Dresden ASIC development center we design ASICs for Bosch Sensortec. In this role you will be responsible for the physical implementation of complex digital designs within mixedsignal SoC ASICs for consumer applications.
Job description:
- Create something new: You will work in interdisciplinary teams taking responsibility for full RTL2GDS flow including Synthesis Place & Route Physical Design Verification and Design for Testability
- Reliable implementation: You will help to ensure first time right IC designs by generating robust timing constraints for synthesis and processing of powerful signoffchecks such as LogicEquivalenceCheck (LEC) and static timing analysis (STA) on toplevel; You will ensure power integrity by executing electromigration (EM) and IRdrop analysis and product quality by Automatic Test Pattern Generation (ATPG)
- Think holistically: You understand design requirements derive constraints create physical implementations at gate level verify timing requirements on postlayout netlists and create documentation in accordance with the design; For this you will collaborate closely with the architecture digital layout and analog teams
- Networked communication: You will work in an international and globally distributed team of experts
- Conscientious coordination: You will support us in continuously improving our Physical Design methodology flow and verification strategies
Qualifications :
- Personality: Strong problemsolving mindset with a high level of technical curiosity and a drive to stay at the forefront of physical design technologies
- Working Practice: Independent detailoriented and qualitydriven working style with strong team collaboration skills in complex project environments
- Experience: 3 to 5 years of industry experience or a fitting PhD are mandatory; High expertise in stateoftheart Physical Design EDA tools preferably in the Synopsys and Ansys tool chains; Strong experience in physical design verification methodologies (e.g. Static Timing Analysis EM/IRdrop analysis) in advanced technology nodes; Deep understanding of low power strategies (clock gating power gating UPF); proficient in integration of DfT (DesignforTest) features for scan testing with sufficient coverage; Profound skills in scripting and programming languages such as TCL and Python; Basic knowledge of Verilog/VHDL hardware description languages is beneficial
- Languages: Proficient in English; additional language skills are a plus
- Education: Degree (././PhD) in electrical engineering or a related field with outstanding academic results
Additional Information :
We offer great opportunities for mobile working as well as different parttime models or jobsharing. Feel free to contact us.
Diversity and inclusion are not just trends for us but are firmly anchored in our corporate culture. Therefore we welcome all applications regardless of gender age disability religion ethnic origin or sexual identity.
Bosch Sensortec GmbH is looking forward to your application!
Need support during your application
Samuel Zinn (Human Resources)
Need further information about the job
Christoph Tzschoppe (Functional Department)
Remote Work :
No
Employment Type :
Fulltime
Employment Type
Full-time
