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You will be updated with latest job alerts via email5-7years
Not Disclosed
Salary Not Disclosed
1 Vacancy
ACG2724JOB
Our client is a leading semiconductor manufacturing company who is looking for a qualified candidate to join their firm.
Create custom layout designs for a wide range of analog and mixedsignal components including power regulators (LDOs) reference circuits (Bandgap) data converters (ADC/DAC) PLLs SerDes clock recovery circuits equalizers drivers and I/O interfaces.
Work in close coordination with analog circuit and physical design teams to meet performance electrical and arearelated specifications.
Conduct layout optimization targeting power integrity (IR) electromigration limits signal integrity and ensure full DRC/LVS compliance.
Perform DRC LVS ERC and PEX verification using EDA tools like Calibre.
Follow foundryspecific layout rules (e.g. TSMC Samsung) and support leadingedge nodes from 28nm down to 2nm including FinFET and GAAFET technologies.
Participate in tapeout processes layout debugging and workflow improvements.
Bachelor s degree or higher in Electrical Engineering Microelectronics Semiconductor or related fields.
5 years of handson experience in custom IC layout.
Solid working knowledge of layout tools (Cadence Virtuoso Synopsys Custom Compiler).
Handson experience with Calibre DRC/LVS/PEX ICV DRC/LVS StarRCXT.
Strong grasp of analog layout concepts such as device matching shielding strategies centroid layout guard ring usage and dummy placement.
Experience with advanced nodes (FinFET: 4nm 14nm; GAAFET: 2nm 3nm) is a plus.
Familiarity with scripting (Skill Python Tcl Perl) is an advantage.
Strong communication skills teamwork independence and a high level of responsibility.
Contact: Thang Nguyen or Giau Nguyen
Due to the immense number of applications only shortlisted candidates will be contacted.
Full Time