Position Name Low Power SoC Verification
Experienced in ASIC/SoC verification with 4 years focusing on lowpower design. Proficient in SV UVM poweraware simulation and tools like Synopsys Cadence and Mentor for power analysis. Skilled in lowpower design techniques (e.g. clock gating power gating DVFS) and UPF/CPFbased verification. Familiar with scripting languages (Python Perl TCL) for automation and power optimization techniques. Knowledgeable in functional safety standards like ISO 26262 for automotive applications.
Experience:
- 4 years of experience in ASIC/SoC verification with a focus on lowpower design verification.
- Solid Experience on SV UVM
- Handson experience with poweraware simulation and verification tools.
- Familiarity with lowpower design techniques such as clock gating power gating and dynamic voltage/frequency scaling (DVFS).
- Proficiency in lowpower UPF/CPFbased verification
- Familiarity with EDA tools for power analysis and verification (e.g. Synopsys Cadence Mentor).
Preferred Qualifications:
- Experience with scripting languages like Python Perl or TCL for automation.
- Knowledge of power estimation and optimization techniques.
- Familiarity with functional safety standards (e.g. ISO 26262 for automotive applications)
tcl,asic/soc verification,power estimation,cadence,dynamic voltage/frequency scaling (dvfs),python,power gating,upf/cpf,eda,sv uvm,iso 26262,power-aware simulation,perl,asic/soc,clock gating,mentor,optimization techniques,low-power design,synopsys,upf/cpf-based verification,scripting languages,performance analysis