ASIC Verification Engineer

OTSI

Posted on : 26-04-2025

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1 Vacancy

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Job Location

San José - Costa Rica

Monthly Salary

Not Disclosed

Salary Not Disclosed

Vacancy

1 Vacancy

Posted on : 26-04-2025

Job Description

System Verilog and Specman language.

UVM methodologies

Test Plans and using logic simulation

Coding test cases and checkers

Coverage driven verification

Digital state machine architecture and logic design

simulationbased debug

Testbench development

Requirements

Bachelors degree in Electrical Electronic or Computer Engineering

Advanced English level

Soft Skill

Good communication and problem solving

Proactive and selfdirected

Teamwork

Employment Type

Full Time

Company Industry

Key Skills

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About Company

OTSI

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