Hardware Engineer High-speed IO design Cadence Allegro Altium Simulation
Hardware Engineer High-speed IO design Cadence Allegro Altium Simulation
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1 Vacancy
Job Description
About Marvell
Marvells semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise cloud and AI automotive and carrier architectures our innovative technology is enabling new possibilities.
At Marvell you can affect the arc of individual lives lift the trajectory of entire industries and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation above and beyond fleeting trends Marvell is a place to thrive learn and lead.
Your Team Your Impact
As a Senior Staff Engineer in Test Development within the Operations business group you will be responsible for testing features on Marvells silicon semiconductor chips for both internal and external customers ensuring only highperforming units are shipped. Youll work closely with the design team to ensure all chip features are fully testable and meet customer specifications. In cases where our chips exceed the capabilities of current testing equipment you may need to develop innovative testing strategies or write new code to maintain performance standards.What You Can Expect
Inhouse Design Simulation and BOM Management.
Direct collaboration with TE/DE/SE teams within Marvell.
Enhance design accuracy before fabrication.
Shorten the design cycle time.
Standardize ATE Load Board Design Flow.
Develop templates and BestKnown Methods (BKM) for ATE load board design.
Source and manage critical highcost components.
Outsource fabrication and assembly to vendors with proven records of cost efficiency fast cycle times and consistent SI/PI performance as well as highquality fabrication and assembly standards.
What Were Looking For
3 to 10 years of experience as an Electrical Engineer specializing in highspeed IO design on complex highdensity printed circuit board assemblies for ATE applications including ASIC ODSP CDSP Switch HDD PreAmp and Processors.
Extensive experience in managing ATE load board vendors and coordinating production timelines.
Deep understanding of Signal Integrity (SI) and Power Integrity (PI) design principles.
Skilled in simulation technologies with handson proficiency.
Demonstrated ability to collaborate effectively with crossfunctional teams including test design verification and product engineering.
Strong knowledge of mechanical and thermal components and their integration in ATE load board design.
Experienced with Cadence Allegro and Altium for schematic and layout design.
Excellent analytical and problemsolving abilities.
Bachelors degree in Electrical Engineering.
Expected Base Pay Range (USD)
$ per annumThe successful candidates starting base pay will be determined based on jobrelated skills experience qualifications work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
At Marvell we offer a total compensation package with a base bonus and and financial wellbeing are part of the package. That means flexible time off 401k plus a yearend shutdown floating holidays paid time off to volunteer. Have a question about our benefits packages health or financial Ask your recruiter during the interview process.All qualified applicants will receive consideration for employment without regard to race color religion sex national origin sexual orientation gender identity disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at .
#LIRS1Employment Type
Full-Time
