Principal Product Engineer - RTL Design
Principal Product Engineer - RTL Design
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Job Description
At Cadence we hire and develop leaders and innovators who want to make an impact on the world of technology.
Job Title: Principal Product Engineer
Location: NOIDA
Cadence is a pivotal leader in electronic design building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software hardware and IP that turn design concepts into reality. Cadence customers are the worlds most innovative companies delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer hyperscale computing 5G communications automotive aerospace industrial and health.
The Cadence Advantage
- The opportunity to work on cuttingedge technology in an environment that encourages you to be creative innovative and to make an impact.
- Cadences employeefriendly policies focus on the physical and mental wellbeing of employees career development providing opportunities for learning and celebrating success in recognition of specific needs of the employees.
- The unique One Cadence One Team culture promotes collaboration within and across teams to ensure customer success
- Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests
- You get to work with a diverse team of passionate dedicated and talented individuals who go above and beyond for our customers our communities and each otherevery day.
Job Summary
Drive key customer engagements in cooperation with local/international Field Applications team Interface with R&D team to drive and influence product development to fulfill customer requirements. Candidate should have a good knowledge of RTL design verification gate level simulation timing & System Verilog. Knowledge about static timing analysis tool SDC constraints is a plus. This position requires an engineer passionate about learning and diagnosing verification problems systematically to improve throughput to verify and debug cuttingedge SOCs System ICs and complex Ips.
Job Responsibilities
To drive deployment of latest innovations in verification automation with leading partners/customers as well as architecting solutions and products to add significant value for the SVG at Cadence. This position requires an engineer passionate about learning and diagnosing verification problems systematically to improve throughput to verify and debug cuttingedge SOCs System ICs and complex Ips. The candidate should have knowledge of Gate Level simulation timing RTL design verification.
Experience and Technical Skills required
- 7 to 11 years experience in diagnosing verification problems systematically to improve throughput to verify and debug cuttingedge SOCs System ICs and complex Ips.
- Should have experience in deployment of latest innovations in verification automation with leading partners/customers
- Having a knowledge of SDC (timing constraints) liberty files Static timing analysis is a plus
Qualifications
- BE/BTech/ME/MS/MTech in Electrical/Electronics
Behavioral skills required
- Must possess strong written verbal and presentation skills
- Ability to establish a close working relationship with both customer peers and management
- Explore whats possible to get the job done including creative use of unconventional solutions
- Work effectively across functions and geographies
- Push to raise the bar while always operating with integrity
Were doing work that matters. Help us solve what others cant.
Required Experience:
Staff IC
Employment Type
Full-Time
