Logic RTL Design Engineer 106383

What you do at AMD changes everything

At AMD we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in highperformance computing graphics and visualization technologies building blocks for gaming immersive platforms and the data center.

Developing great technology takes more than talent: it takes amazing people who understand collaboration respect and who will go the extra mile to achieve unthinkable results. It takes people who have the passion and desire to disrupt the status quo push boundaries deliver innovation and change the world. If you have this type of passion we invite you to take a look at the opportunities available to come join our team.

• Logic RTL Design Engineer Member of Technical Staff

  The Role:

  AMDs Low Power Advanced Development team is seeking talented selfmotivated individuals to help develop low power innovations that enable industryleading power efficient computing and graphics products. We have openings for R&D engineers to serve as key contributors in small project teams working on low power advanced development projects.

  The Person:

  A candidate who is seeking challenging projects in low power design using the latest modern semiconductor technologies who is eager to learn and is a good team player

  Key Responsibilities:

• Logic RTL design for custom mixedsignal circuits in advanced CMOS technologies.
• Design logic blocks in Verilog for optimal performance/area/power.
• Closely work with Physical Design teams and IP and SoC level to optimize implementation enable SoC integration close timing and solve any issues that arise through the design cycle.
• Create individually or in collaboration with other team members design reviews technical reports and other documentation required for meeting the design quality and for the tapeout signoff.
• Working with design leads to understand features to be implemented and verified.
• Initial verification and debugging test failures.
• Design documentation and verification plan creation.
• Specifying coverage points reviewing functional and code coverage results and assisting to increase coverage.
• Provide support in simulation emulation and silicon environments.

• Preferred Experience:

• Must have experience in RTL level ASIC design including use of a source control system and RTL linting tools as well as be able to debug RTL code using simulation tools.
• Must be expert in Verilog and proficient in System Verilog VerilogA C/C Perl TCL Unix shell scripting and working in Linux and Windows environments.
• VCS/Verdi experience is a plus..
• Must be able to understand create and debug STA constraints.
• Strong understanding of synthesis P&R and clock domain crossing design methodologies.
• Experience with clock generators such as PLL and FLL.
• Strong analytical thinking and problem solving skills excellent attention to detail and good coding skills and style required.
• Understanding of basic analog blocks (Linear and Switching voltage regulators DAC ADC comparators oscillators high speed circuits) as well as analog/mixed signal design concepts and CMOS processes are a plus.
• Familiarity with Cadences custom IC design environment and spice electrical simulators is a plus.
• Strong communication skills teamwork experience and a quick learner in a fastmoving environment.

• Academic Credentials:

• MS w/ 5 year experience or PhD Electrical Engineering and/or Computer Architecture work experience.

• Location:

  Austin TX

• • • AMD employees who will be working onsite at an AMD US facility are encouraged to provide proof of being fully vaccinated against COVID19 upon their start date. This is for the safety of our employees and to permit AMD to be prepared in the event the stay on Executive Order 14042: Ensuring Adequate COVID Safety Protocols for Federal Contractors is lifted. AMD is not requiring exemption / accommodation submittals at this time.

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