Job Description Summary
This Architect will be responsible for guiding and developing Magnetic Resonance Imaging (MRI) Receive Chain hardware as a digital design expert. This individual will contribute technically through FPGA design ASIC design and integration and schematic/layout definition and review. This individual will also lead hardware strategy for the Receive subsystem working with and mentoring team members to realize hardware solutions and solve technical problems.
This is a hybrid role: minimum 3 days / week in person Waukesha WI
Job Description
Essential Responsibilities
- Duties include (but are not limited to):
- Guide Receive Chain hardware development working with team to productize circuit boards & assemblies implementing FPGAs ADCs ASICs analog signal conditioning circuits etc.
- Contribute to designs as a digital design subject matter expert selecting FPGA strategy writing VHDL designing robust simulation and test bench solutions etc.
- Scope and define ASIC test and verification plans ensuring test coverage & debugging are key parts of initial designs.
- Update knowledge and skills to keep up with industry advancements in FPGA / IC design and translate new developments into concepts / prototypes.
- Write detailed functional specifications that document newly created designs and support product introduction.
- Provide technical support to team throughout product development and implementation process.
- Provide input requirements & definition to firmware team to develop lowlevel drivers for communication links.
- Engaging in all phases of new product introduction: concept architecture documentation design prototype test supplier interfaces manufacturing introduction and service support.
Qualifications/Requirements
- BS in Electrical Engineering or similar with at least 10 years of digital design experience. Minimum of 2 years MRI industry experience.
- Experience in FPGA design (Altera/Intel Xilinx/AMD Lattice) including ownership of complex designs implementing the following features (or equivalents): DSP High Speed Serial interfaces (JESD LVDS PCIe etc) PLLs etc.
- Familiarity with ASIC development process and digital ASIC (System Verilog/VHDL) design / simulation tools including test bench definition
- Demonstrated experience in MATLAB or equivalent simulation/modeling tool
- Working knowledge of project management processes and procedures.
- Experience with related electrical test equipment such as oscilloscopes spectrum analyzers logic analyzers bit error rate tester
Desired Characteristics
- Masters degree or PhD in Electrical Engineering or similar.
- 15 years relevant work experience.
- 10 years with a Healthcare imaging modality and working in a highly regulated environment.
- Experience with full ASIC development process; bringing up and debugging ASICs.
- Demonstrated experience in design of standard bus formats such as PCIe CAN Ethernet LVDS
- Signal Integrity simulation and review experience
- Experience with sensitive analog signal chains (designs leveraging preamps cascade modeling etc)
- Demonstrated selfstarter energizing results oriented and able to multitask
- Excellent teamwork coordination and communication skills
- Experienced in developing project plans and estimates
- Effective oral and written communication skills
- EMC compatible design/solution experience
- Design for Reliability and Manufacturability experience
- Working knowledge of GEHC tools and processes EQPM MyWorkshop Cadence
- DFSS or Green Belt/Black Belt Certified (Six Sigma Design/Quality)
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GE HealthCare will only employ those who are legally authorized to work in the United States for this opening. Any offer of employment is conditioned upon the successful completion of a drug screen (as applicable).
While GE HealthCare does not currently require U.S. employees to be vaccinated against COVID19 some GE HealthCare customers have vaccination mandates that may apply to certain GE HealthCare employees.
Relocation Assistance Provided: Yes