Senior RTL Verification Lead / RTL Verification Engineer
Are you an experienced RTL Verification professional looking for your next challenge Look no further!
Qualifications:
- BE/ME/MTech/MS in Electrical Engineering
- 6 to 12 years of RTL verification experience for the Senior RTL Verification Lead position
- 4 to 5 years of relevant industry experience for the RTL Verification Engineer position
- Proficiency in advanced verification methodologies like UVM/OVM/VMM/System Verilog
- Experience in constrained random stimulus generation assertionbased verification and functional coverage techniques.
- Knowledge of register verification standards NLP/GLS verification flows
- Strong experience in IP level and subsystem level verification on protocols such as PCIE UCIe HBM etc.
- Relevant experience in enabling and verifying controller interoperability testing at the subsystem level is a plus
Responsibilities:
- Lead a highly motivated verification team responsible for DV for IPs like UCIe HBM PCIe Bus logic etc. (Senior RTL Verification Lead)
- Implement advanced verification methodologies such as UVM/OVM/VMM/System Verilog
- Generate constrained random stimulus and perform assertionbased verification.
- Ensure functional coverage techniques are applied effectively.
- Apply register verification standards and NLP/GLS verification flows.
- Conduct IP level and subsystem level verification on protocols like PCIE UCIe HBM etc.
- Enable and verify controller interoperability testing at the subsystem level.
Experience:
- 6 to 12 years of RTL verification experience for the Senior RTL Verification Lead position
- 1 to 3 years of relevant industry experience for the RTL Verification Engineer position
If you meet the qualifications and are ready to make a difference apply now! Send your resume to
#RTLVerification #SeniorRTLVerificationLead #ASICDesign #VerificationMethodologies #PCIe #UCIe #HBM #JobOpportunity #HiringNow #JoinOurTeam
Required Experience:
Manager