Design Verification Intern - Bachelors
Design Verification Intern - Bachelors
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Job Description
About Marvell
Marvells semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise cloud and AI automotive and carrier architectures our innovative technology is enabling new possibilities.
At Marvell you can affect the arc of individual lives lift the trajectory of entire industries and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation above and beyond fleeting trends Marvell is a place to thrive learn and lead.
Your Team Your Impact
Infrastructure Processor Business Unit a part of Networking and Processor Business Group encompasses OCTEON and the awardwinning OCTEON FusionM product families. The SoC family of multicore CPU processors and Radio Access SoCs offer bestinclass performance low power rich software ecosystem virtualization features and open source application support with highly optimized custom ARM CPU cores providing an excellent solution for a highly flexible endtoend optimized 5G platform.As part of the Infrastructure Processor unit at Marvell you will verify all of the circuitry that goes inside our chips for the general market and for specific customers. These chips use cuttingedge technology to facilitate data transfers at high speeds and you will help verify that each design meets our customers specifications whether theyre a major telecom organization or automotive company etc.
What You Can Expect
In this inoffice role in Austin youll work day to day with an RTL engineer to verify their design. Their design is in Verilog; youll use System Verilog to debug. Youll run simulations using Synopsys VCS or a similar program and then debug as needed until the design meets required specifications. Youll also work closely with DFT engineers who are working in parallel on your blocks.
Youll attend weekly staff meetings to go over what everyone is working on and update your progress or address any issues. As you take responsibility for larger blocks you may have to present to a review committee and explain your test plan and test schedule for those larger blocks.
What Were Looking For
To be successful in this role you must:
- Be pursuing a Bachelors Degree in Electrical Engineering or Computer Engineering.
- Your coursework must include some analog classes Verilog or VHDL basic circuits and computer architecture. You should have a focus in VLSI or show projects in your courses that directly relate to chip design.
- You have used a tool like Synopsys Cadence or Mentor to run simulations and you can write and debug a testbench.
- Be comfortable working in a Linux environment and doing scripting with Python.
- Be extremely detailoriented and ready to iterate a design over and over again until it is refined completely.
- Work and communicate well with your team keeping them in the loop about your progress issues you encounter and any deviations from the planned schedule.
Expected Base Pay Range (USD)
28 55 $ per hour.The successful candidates starting base pay will be determined based on jobrelated skills experience qualifications work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
For Internship roles we are proud to offer the following benefits package during the internship medical dental and vision coverage perks and discount programs wellness & mental health support including coaching and therapy paid holidays paid volunteer days and paid sick time. Additional compensation may be available for intern PhD candidates.All qualified applicants will receive consideration for employment without regard to race color religion sex national origin sexual orientation gender identity disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at .
#LIAR2Required Experience:
Intern
Employment Type
Full-Time
