Digital Verification Engineer

We areSilicon Labs.We are a leader in secure intelligent wireless technology for a more connected world.Our integrated hardware and software platform intuitive development tools unmatched ecosystem and robust support make us the ideal longterm partner in building advanced industrial commercial home and life applications. We make it easy for developers to solve complex wireless challenges throughout the product lifecycle and get to market quickly with innovative solutions that transform industries groweconomiesand improve lives.

Digital Verification Engineer
Austin TX

Meet the Team
We are focused on producing worldclass Wireless MCU products. The architecture specification design verification emulation and implementation of the Wireless MCU SoCs are all the responsibilities of our team. The IPs on our chip include an embedded CPU system with analog and digital peripherals advanced security advanced power management and best in class low power wireless modems. We strive to provide advanced technology solutions through innovation in custom RISCV Cores and AI/ML accelerators.

Digital Verification Engineer

The position involves owning verification of critical wireless IP/SS/SoC components using a combination of simulation and formal verification techniques. The qualified candidate should have built C/UVM test benches from scratch and taken themthrough all stages of . The candidate will work with Architects and cross functional teams to deliver comprehensive verification strategy along side system level debug . The candidate will get exposure to AMS and DMS verification in this role to help expand his/her verification knowledge base

Responsibilities

• IP/SS/SoC Verification for breakthrough wireless designs
• Create and execute the test plan with emphasis on metrics driven verification
• Constrained random tests scoreboard and coverage development
• Power Architecture Verification including low power modes with UPF
• Apply formal verification tools like lint auto and property checks
• DMS AMS & System Level Verification& Debug pre/post silicon
• GLS & Power Analysis
• Architect and implement Verification Components using C/UVMbased methods
• Develop verification flows and methodologies to enhance IP SoC and Formal Verification

Skills You Will Need:

• 8 years in Industry
• Bachelors or Masters degree in Electrical/Computer Engineering
• Strong knowledge of Verilog SystemVerilog UVM and C/C
• Knowledge of digital design ARM or RISCV architecture and bus protocols
• Knowledge of scripting languages like Perl Python Tcl and shell
• Advanced verification skill in SVAs constrained random stimulus and coverage analysis
• Cbased testcase development and debugging skills
• Verify and debug lowpower design with UPF

The following qualifications will be considered a plus:

• Debug SDF Back Annotated Gate Simulations
• Mentoring and leadership skills
• Exceptional problemsolving skills
• Good written and oral communication skills
  

Benefits & Perks

You can look forward to the following benefits:

• Great medical (Choice of PPO or Consumer Driven Health Plan with HSA) dental and vision plans
• Highly competitive salary
• 401k plan with match and Roth plan option
• Equity rewards (RSUs)
• Employee Stock Purchase Plan (ESPP)
• Life/AD&D and disability coverage
• Flexible spending accounts
• Adoption assistance
• BackUp childcare
• Additional benefit options (Commuter benefits Legal benefits Pet insurance)
• Flexible PTO schedule
• 3 paid volunteer days per year
• Charitable contribution match
• Tuition reimbursement
• Free downtown parking
• Onsite gym
• Monthly wellness offerings
• Free snacks
• Monthly company updates with our CEO
  

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We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race religion color national origin gender sexual orientation age marital status veteran status or disability status.