Principal FPGA Design Engineer

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Cadenceis a pivotal leader in electronic design building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software hardware and IP that turn design concepts into reality. Cadence customers are the worlds most innovative companies delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer hyperscale computing 5G communications automotive aerospace industrial and health.

The Cadence Advantage

• The opportunity to work on cuttingedge technology in an environment that encourages you to be creative innovative and to make an impact.
• Cadences employeefriendly policies focus on the physical and mental wellbeing of employees career development providing opportunities for learning and celebrating success in recognition of specific needs of the employees.
• The unique One Cadence One Team culture promotes collaboration within and across teams to ensure customer success
• Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests
• You get to work with a diverse team of passionate dedicated and talented individuals who go above and beyond for our customers our communities and each otherevery day.

Job Responsibility

Protium is leading product in FPGA Emulation/Prototyping domain. This role is to design verification timing closure and hardware validation of the FPGA IPs.

• Developing fieldprogrammable gate array intellectual properties (FPGA IPs) for Protium platform including design verification integration timing closure documentation and releasing the IPs to end users;
• Working on FPGA IP Design Verification/Simulation Timing closure Validation of IP on the hardware;
• Enhancing current IPs as well as developing new IPs.
• Debug and fix internal regression failures for FPGA IPs.
• Documentation of IPs

Position Requirements/Qualifications:

• Master degree in Electrical Engineering with 5 years of experience
• Experience with FPGA design and verification using Verilog
• Experience with high end Xilinx(AMD) FPGAs including using Vivado tool for simulation Place and route
• Experience in debugging FPGAs in the lab using Vivado hardware manager debugging with firmware/software
• Experience using Linux servers Script development using Shell/Perl/TCL
• Experience using Cadence Simulators Incisive or Xcelium
• Detailed knowledge about industry standard interfaces such as PCI Express DRAM/DDR4 SRAM I2C JTAG AXI

The annual salary range for California is $131600 to $244400. You may also be eligible to receive incentive compensation: bonus equity and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications skill level competencies and work location. Our benefits programs include: paid vacation and paid holidays 401(k) plan with employer match employee stock purchase plan a variety of medical dental and vision plan options and more.

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