PCIE Engineer
PCIE Engineer
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1 Vacancy
Job Description
Job Title: PCIe Engineer (Peripheral Component Interconnect Express)
Location: Santa Clara CA (Hybrid)
Duration: Long Term Contract
Domain: Engineering
Required Skills: Presilicon verification / UVM methodology
Key Responsibilities:
Architect develop and use simulation and/or formalbased verification environments at IP and SoClevel.
Lead and manage verification teams including planning tracking verification closure and delivery to programs.
Develop and execute comprehensive verification plans including testbenches and test cases.
Collaborate with design architecture and software teams to define and implement verification strategies.
Utilize advanced verification methodologies including UVM.
Mentor and guide junior engineers fostering a collaborative and innovative team environment.
Preferred Experience:
10 years of senior Presilicon verification engineer with PCIE physical link layer experience in typical networking application products.
Require experience with development of UVM and System Verilog test benches and usage of simulation tools/debug environments such as Synopsys VCS or Cadence Xcelium.
Require strong understanding of state of the art of verification techniques including assertion and metricdriven verification.
Require familiarity with verification management tools.
Prior years of experience in presilicon validation within the semiconductor industry
Demonstrated ability to grasp new technical concepts quickly
Experience with IP/System level bringup SOC debug techniques and methodologies
Strong analytical/problem solving skills and pronounced attention to details
Excellent written and verbal communication skills
Selfstarter strong collaborator and able to independently drive tasks to completion
Strong organizational skills and ability to handle multiple issues at the same time
Thanks & Regards
Anmol Jaiswal
Phone :
EMail :
Employment Type
Full Time
