Principal Engineer High-Speed SerDes System Architect
Principal Engineer High-Speed SerDes System Architect
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Job Description
We are looking for a Principal Engineer HighSpeed SerDes System Architect to lead nextgen highspeed wireline electrical communication research. Join our HighSpeed HighFrequency team within the Board Engineering Lab at our Grenoble Research Center collaborating closely with HQ technical teams in China to develop 112 Gbit/s SerDes systems.
Location: Grenoble Research Center (Onsite)
Salary:per annum
Employment Type: Permanent
Key Responsibilities
HighSpeed Research & Innovation Lead research in highspeed wireline electrical communications developing new system architectures designs models & simulations
NextGen SerDes Development Explore SerDes PHY architectures (signaling equalization FEC) for hyperscale data centers & AI infrastructure
Algorithm Development Optimize complex parameter spaces through advanced algorithm modeling
Industry Collaboration Work with universities research institutions & industry partners participating in IEEE OIF conferences & standards organizations
Technology Roadmap Definition Develop longterm highspeed interconnect strategies & project planning
Mentorship & Leadership Supervise interns PhD students & engineers providing technical guidance
What You Bring
Masters/PhD in Electrical Engineering Communication Engineering Information Technology or Signal Processing
10 years of experience in highspeed wireline electrical communication
Deep expertise in modulation equalization synchronization & forward error correction
Proven experience in SerDes architecture (serializer deserializer) for 56 Gbps 112 Gbps NRZ & PAM applications
Signal Integrity Expert Strong background in highspeed link analysis
Preferred Skills
Industry Standards Knowledge of IEEE 802.3 OIFCEI InfiniBand CEI224G
Advanced Signaling Understanding of highorder modulation (PAM) singleended & bidirectional signaling
SerDes Protocols Experience with DDR PCIe and other highspeed interfaces
Hardware Design Indepth knowledge of SerDes ASICs DSPs PCBs connectors packaging
Academic & Industry Engagement Participation in technical conferences & research projects
Innovative Mindset Passion for technology problemsolving & highspeed system architecture
Technical Tools & Work
SerDes Modeling & Simulation Python (preferred) MATLAB VerilogA ADS
Signal Integrity Tools ADS custom models (MATLAB Python)
Why Join Us
Work on 112 Gbit/s SerDes systems Cuttingedge technology & highimpact research
Global Collaboration Partner with top engineers & researchers worldwide
Industry & Research Engagement Work with leading institutions & participate in global conferences
Shape the Future Define the roadmap for nextgeneration highspeed communications
Ready to push the limits of highspeed signal integrity Apply now!
#SerDes #HighSpeedDesign #SignalIntegrity #HardwareEngineering #ICTIndustry #HiringNow
Employment Type
Full Time
