Job Summary:
Design and develop critical analog mixedsignal custom digital block and full chip level integration support.
Responsible for layout verification tasks such as LVS/DRC/Antenna quality check and documentation.
Ensure ontime delivery of blocklevel layouts with acceptable quality.
Contribute to effective project management.
Communicate efficiently with engineering teams in the India US and Japan to ensure the success of the layout project.
Have 13 years of experience in analog/custom layout design in advanced CMOS process.
Expert in Cadence VLE/VXL and Calibre DRC/LVS.
Have handson experience in Critical Analog Layout design of blocks such as Temperature sensor PLL ADC DAC LDO Bandgap Ref Generators Charge Pump Current Mirrors Comparator Differential Amplifier etc.
Have good understanding of Analog Layout fundamentals such as Matching Electromigration Latchup coupling crosstalk IRdrop active and passive parasitic devices etc.
Understand layout effects on the circuit such as speed capacitance power and area etc.
Ability to understand design constraints and implement highquality layouts.
Possess strong command and problemsolving skills in Physical layout verification.
Have good understanding of basic active and passive devices such as RL C and MOSFETs.
Scripting and automation experience is a plus but not mandatory.
Have excellent verbal and written communication skills.