Analog Layout Trained Fresher

• Excellent work experience in Analog / Mixed Signal Layout design in advanced FinFET processes like 16nm 12nm 10nm 7nm 5nm 3nm
• Expertise on complete PNR flow CTSrouting Timing Closure.
• Hands on experience in any or multiple critical blocks such as SERDES PHY HDMI PLL ADC DAC LDO Bandgap Ref Generators Charge Pump Current Mirrors Comparator Differential Amplifier etc.
• Excellent understanding of CMOS / BiCMOS / SOI / FinFET process
• Excellent understanding of CMOS / BiCMOS / SOI / FinFET process
• Experience in AMS IP integration in full chip according to the guidelines demanded by the Full Chip needs
• Excellent problemsolving skills in Routing Congestion Physical Verification in Custom Layout
• Sound knowledge and experience for verification checks like DRC / LVS / ERC / Antenna / LPE / DFM etc.
• Knowledge of various analog layout techniques understanding of various circuit principles as affected by Layouts such as speed capacitance power noise and area
• Excellent handson experience in industry standard layout and verification tools in a Linux environment of Cadence and Mentor EDA tools. Power user of VirtuosoXL
• Excellent Leadership skills and Mentor & guide team members in execution of Layout and review their work outputs for quality and delivery
• Responsible for timely and quality execution of Custom Layout design
• Excellent communication skills and proactive at work

layout,layout design,very-large-scale integration (vlsi)