StaffSenior Staff Principal Engineer, Design Verification

• Be a part of endtoend verification execution for SOC owning complex digital IPs and subsystems from specification to signoff
• Define and drive IPlevel verification strategies including test plans coverage models and closure criteria
• Develop scalable reusable UVMbased verification environments for IP and subsystem verification
• Lead functional code assertion and crosscoverage closure ensuring highquality signoff with clear metrics
• Apply AI/MLassisted verification techniques to accelerate coverage convergence identify stimulus gaps and optimize regression efficiency
• Drive constraint random and directed test methodologies for thorough protocol cornercase and stress verification
• Collaborate with RTL Architecture Emulation and SoC Verification teams to ensure seamless IP integration
• Review IP specifications and work with architects to translate requirements into robust verification plans and checkers
• Develop and deploy advanced checkers scoreboards assertions (SVA) and protocol monitors
• Work with EDA vendors to evaluate and adopt nextgeneration verification coverage and analytics tools
• Mentor junior engineers and promote bestinclass verification practices and continuous improvement
• Support GateLevel Simulation (GLS) lowpower verification and postsilicon debug when required.
• Ensure IP deliverables meet quality schedule and reusability expectations for SoC integration.

Qualifications :

• Bachelors or masters degree in Electronics Engineering
• 5-15 years of experience in SoC Verification domains and have working knowledge of industry standard EDA toolkits.  
• Strong expertise in UVMbased testbench architecture and development
• Proven experience in metricdriven verification including functional and code coverage closure
• Deep understanding of SystemVerilog UVM assertions (SVA) and verification best practices
• Experience with directed and constrainedrandom verification methodologies
• Experience debugging complex design issues in simulation emulation and postsilicon environments
• Proficiency in Verilog/SystemVerilog with working knowledge of C/C Shell scripting
• Strong analytical problemsolving and communication skills

Preferred/Plus Qualifications

• Handson experience using AI/MLbased verification tools for:
  • Coverage gap analysis
  • Test stimulus optimization
  • Regression triage and coverage acceleration
• Scripting expertise in Python Perl or TCL for automation and analytics
• Exposure to formal verification and hybrid formalsimulation flows
• Familiarity with highspeed or complex IPs such as:
  • H.264
  • Security debug or safetycrititical

Additional Information :

Renesas is an embedded semiconductor solution provider driven by its Purpose To Make Our Lives Easier. With a global team of over 21000 engineers and problem solvers in more than 30 countries we offer the opportunity to work on worldleading technology for Automotive Industrial Infrastructure and IoT shaping a safer healthier greener and smarter future.

At Renesas TAGIE is our culture grounded in being Transparent Agile Global Innovative and Entrepreneurial. It shapes how we work grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.

We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.

Are you ready to join our team and shape the future with us

Renesas Electronics is an equal opportunity and affirmative action employer committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex race religion national origin gender gender identity gender expression age sexual orientation military status veteran status or any other basis protected by law. For more information please read our Diversity & Inclusion Statement.

Remote Work :

No

Employment Type :

Full-time