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StaffSenior Staff Engineer, Synthesis & Timing Constraints


Job Location:

Bengaluru - India

Monthly Salary: Not provided by the employer
Posted: 8 September 2026 (Yesterday)
Application Deadline: 6 December 2026
Vacancies: 1 Vacancy

Job Summary

We are looking for an experienced Synthesis and Timing Constraints Engineer to join our ASIC/SoC Implementation this role you will lead timing constraint development and synthesis methodologies for complex SoC designs working closely with Architecture RTL Design Physical Design and STA teams to deliver high-quality implementations across advanced technology nodes.

Key Responsibilities

  • Define develop and maintain timing constraints (SDC) at IP subsystem and chip levels.
  • Drive RTL synthesis and optimization using Synopsys Design Compiler and Fusion Compiler.
  • Analyze and resolve timing area power and implementation challenges to achieve design targets.
  • Collaborate with cross-functional teams to ensure robust design convergence throughout the implementation cycle.
  • Develop and enhance methodologies flows and automation to improve productivity and design quality.
  • Support timing closure activities and drive best practices for synthesis and constraint management.
  • Debug and resolve synthesis and timing-related issues during project execution.
  • Contribute to flow improvements for advanced-node ASIC/SoC development.

Qualifications :

  • Bachelors or Masters degree in Electronics Engineering or Electrical Engineering.
  • 10-15 years of experience in ASIC/SoC implementation.
  • Expert knowledge of Synopsys Design Compiler and Fusion Compiler.
  • Strong understanding of Static Timing Analysis (STA) timing closure and SDC methodology.
  • Hands-on scripting experience in Tcl and/or Python.
  • Experience with advanced-node implementation flows.
  • Strong analytical problem-solving and debugging skills.
  • Ability to work effectively with global cross-functional teams.

Preferred Qualifications

  • Experience with low-power design methodologies and optimization techniques.
  • Knowledge of Physical Design and signoff flows.
  • Familiarity with hierarchical and full-chip implementation methodologies.
  • Successful experience supporting complex SoC tapeouts.

Why Join Us

Be part of a high-performing implementation team working on next-generation semiconductor products. Youll have the opportunity to influence methodology drive technical innovation and contribute directly to successful tapeouts on cutting-edge process technologies.


Additional Information :

Renesas is an embedded semiconductor solution provider driven by its Purpose To Make Our Lives Easier. With a global team of over 21000 engineers and problem solvers in more than 30 countries we offer the opportunity to work on worldleading technology for Automotive Industrial Infrastructure and IoT shaping a safer healthier greener and smarter future.

At Renesas TAGIE is our culture grounded in being Transparent Agile Global Innovative and Entrepreneurial. It shapes how we work grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.

We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.

Are you ready to join our team and shape the future with us

Renesas Electronics is an equal opportunity and affirmative action employer committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex race religion national origin gender gender identity gender expression age sexual orientation military status veteran status or any other basis protected by law. For more information please read our Diversity & Inclusion Statement.


Remote Work :

No


Employment Type :

Full-time


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